NDLI: Pipelined fast 2D DCT architecture for JPEG image compression

Content Provider	IEEE Xplore Digital Library
Author	Agostini, L.V. Silva, I.S. Bampi, S.
Copyright Year	2001
Description	Author affiliation: DIMAp, Univ. Fed. do Rio Grande do Norte, Natal, Brazil (Agostini, L.V.)
Abstract	This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole architecture is divided into two I-D DCT calculations by using a transpose buffer. These parts are described in this paper, with an architectural discussion and the VHDL synthesis results as well. The 2-D DCT architecture uses 4,792 logic cells of one Altera Flex10kE FPGA and reaches an operating frequency of 12.2 MHz. One input block with 8/spl times/8 elements of 8 bits each is processed in 25.2 /spl mu/s and the pipeline latency is 160 clock cycles.
Sponsorship	Brazilian Comput. Soc
Starting Page	226
Ending Page	231
File Size	516005
Page Count	6
File Format	PDF
ISBN	0769513336
DOI	10.1109/SBCCI.2001.953032
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-15
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Discrete cosine transforms Transform coding Image coding Two dimensional displays Hardware Logic Field programmable gate arrays Frequency Pipelines Delay
Content Type	Text
Resource Type	Article

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