NDLI: Purely Digital BIST for Any PLL or DLL

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12th IEEE European Test Symposium (ETS'07)

12th IEEE European Test Symposium - Title page

12th IEEE European Test Symposium - Copyright notice

Steering Committee

Program Committee

ETS 2006 Paper Award

Test Technology Technical Council

If It's All about Yield, Why Talk about Testing?

Electronics Design-for-Test: Past, Present and Future

Adaptive Debug and Diagnosis without Fault Dictionaries

DERRIC: A Tool for Unified Logic Diagnosis

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter

Test Configurations for Diagnosing Faulty Links in NoC Switches

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests

Digital Generation of Signals for Low Cost RF BIST

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips

Communication-Centric SoC Debug Using Transactions

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories

PPM Reduction on Embedded Memories in System on Chip

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs

A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus

Selecting Power-Optimal SBST Routines for On-Line Processor Testing

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs

Computation and Application of Absolute Dominators in Industrial Designs

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement

Diagnostic Test Generation Based on Subsets of Faults

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores

Purely Digital BIST for Any PLL or DLL

System-in-Package, a Combination of Challenges and Solutions

Embedded Tutorial: IC Test Cost Benchmarking

Wafer Level Reliability Screens

Embedded Tutorial on Low Power Test

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC

The Eighth IEEE European Test Workshop, 2003. Proceedings.

Proceedings The Seventh IEEE European Test Workshop

IEEE European Test Workshop, 2001.

Proceedings IEEE European Test Workshop

European Test Workshop 1999 (Cat. No.PR00390)

Purely Digital BIST for Any PLL or DLL

Content Provider	IEEE Xplore Digital Library
Author	Sunter, S. Roy, A.
Copyright Year	2007
Description	Author affiliation: LogicVision Inc., San Jose, CA (Sunter, S.; Roy, A.)
Abstract	PLLs are the heart of most SoCs, so their performance affects many tests. Practical, published PLL BIST approaches cannot measure <10 ps RMS jitter or >1 GHz. This paper describes how a SerDes undersampling DFT technique was adapted to test multiple PLLs and DLLs for jitter, output frequency, duty cycle, and other parameters. Its multi-GHz range, sub-picosecond jitter noise floor, and minimal silicon area are better than for any previous silicon-proven DFT or BIST that needs no calibration or analog circuitry. FPGA implementation results are provided.
Starting Page	185
Ending Page	192
File Size	242264
Page Count	8
File Format	PDF
ISBN	0769528279
DOI	10.1109/ETS.2007.35
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-20
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Phase locked loops Jitter Heart Circuit testing Frequency Circuit noise Silicon Calibration Field programmable gate arrays
Content Type	Text
Resource Type	Article

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