NDLI: Architectures for ICT on FPGA

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2015 International Conference on Field Programmable Technology (FPT)

2013 International Conference on Field-Programmable Technology (FPT)

2012 International Conference on Field-Programmable Technology

2011 International Conference on Field-Programmable Technology

2010 International Conference on Field-Programmable Technology

2009 International Conference on Field-Programmable Technology

2008 International Conference on Field-Programmable Technology

2007 International Conference on Field-Programmable Technology

2006 IEEE International Conference on Field Programmable Technology

Proceedings. 2005 IEEE International Conference on Field-Programmable Technology, 2005.

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)

Message from the General Chair and Program Chair

Organising Committee

Program Committee

Table of contents

Programming a hyper-programmable architecture for networked systems

Self-recovery experiments in extreme environments using a field programmable transistor array

Field programmable gate array implementation of a generalized decoder for structured low-density parity check codes

Partial character decoding for improved regular expression matching in FPGAs

Interconnect architectures for modulo-scheduled coarse-grained reconfigurable arrays

Directional and single-driver wires in FPGA interconnect

A greedy algorithm for tolerating defective crosspoints in nanoPLA design

SHAPER: synthesis for hybrid FPGAs containing PLAs using reconvergence analysis

Placement and routing for non-rectangular embedded programmable logic cores in SoC design

QuickRoute: a fast routing algorithm for pipelined architectures

An FPGA-based Othello endgame solver

Real-time detection of line segments using the line Hough transform

gNBX - reconfigurable hardware acceleration of self-organizing maps

Evolvability and reconfigurability

A gate-level model for morphogenetic evolvable hardware

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs

Using multi-bit logic blocks and automated packing to improve field-programmable gate array density for implementing datapath circuits

Stream applications on the dynamically reconfigurable processor

Compiler reuse analysis for the mapping of data in FPGAs with RAM blocks

Memory optimisations for high-resolution imaging

On the placement and granularity of FPGA configurations

Adaptive range reduction for hardware function evaluation

A scalable hardware architecture for prime number validation

Coarsely integrated operand scanning (CIOS) architecture for high-speed Montgomery modular multiplication

Programmable parallel coprocessor architectures for reconfigurable system-on-chip

Windows CE for a reconfigurable system-on-a-chip processor

EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA

Migrating software to hardware on FPGAs

The Quartus University Interface Program: enabling advanced FPGA research

Maximizing system performance: using reconfigurability to monitor system communications

Using function folding to improve silicon efficiency of reconfigurable arithmetic arrays

Low FPGA area multiplier blocks for full parallel FIR filters

Pipelining designs with loop-carried dependencies

Reconfigurable hardware implementation of mesh routing in number field sieve factorization

Fast architectures for FPGA-based implementation of RSA encryption algorithm

Single-chip FPGA implementation of a cryptographic co-processor

Reconfigurable implementation of bit-parallel multipliers over GF(2/sup m/) for two classes of finite fields

Extended genetic algorithm for codesign optimization of DSP systems in FPGAs

FPGA implementation of hierarchical memory architecture for network processors

Evaluating software and hardware implementations of signal-processing tasks in an FPGA

A scalable architecture for elliptic curve point multiplication

An FPGA based prototyping platform for imager-on-chip applications

Compact iterative FPGA Camellia algorithm implementations

An adaptive Viterbi decoder based on FPGA dynamic reconfiguration technology

Single bit error correction implementation in CRC-16 on FPGA

Pre-silicon prototyping of a unified hardware architecture for cryptographic manipulation detection codes

FPGA-acceleration of cone-beam reconstruction for the X-ray CT

Interface adaptor logic - a new model for interfacing peripherals in IP based designs

FPGA implementation of digital upconversion using distributed arithmetic FIR filters

FPGA implementation of a phased array DBF using polyphase filters

FPGA design of HECC coprocessors

A tsume-shogi processor based on reconfigurable hardware

An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs

A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers

Reconfigurable I/O interface for mobile equipments

Domain specific reconfigurable fabric targeting Viterbi algorithm

A new architecture of field programmable analog arrays for reconfigurable instantiation of continuous-time filters

RTOS acceleration on soft-core processors using instruction set customization

A rapid prototyping framework for audio signal processing algorithms

Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits

Achieving wide frequency range in an analog FPGA

3D graphics accelerator platform for mobile devices

Retiming aware clustering for sequential circuits

A scalable and pipelined FPGA implementation of an OC192 WF scheduler

Wavelet spectral dimension reduction of hyperspectral imagery on a reconfigurable computer

Architectures for ICT on FPGA

Design of an imaging system based on FPGA technology and CMOS imager

Study on column wise design compaction for reconfigurable systems

Memory specification for reconfigurable computing synthesis tools

Run-time mapping of applications to a heterogeneous reconfigurable tiled system on chip architecture

An FPGA implementation of a modified version of RED algorithm

A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing

FPGA architecture extensions for preemptive multitasking and hardware defragmentation

Implementation of a flexible RAKE receiver in heterogeneous reconfigurable hardware

An improved Montgomery modular inversion targeted for efficient implementation on FPGA

Hardware/software co-simulation environment for CSoC with soft processors

FPGA implementation of spiking neural networks - an initial step towards building tangible collaborative autonomous agents

Effective system and performance benchmarking for reconfigurable computers

Scalable structured data access by combining autonomous memory blocks

An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory

Switch-box design for synthesizable coarse-grain arrays for system-on-chip applications

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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