NDLI: System on a FPGA Virtual Concatenation

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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

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2008 16th International Symposium on Field-Programmable Custom Computing Machines

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)

The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines - Table of Contents

Parallelization of MATLAB Applications for a Multi-FPGA System

Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems

Parameterized Module Generator for an FPGA-Based Electronic Cochlea

Novel Algorithm Combining Temporal Partitioning and Sharing of Functional Units

Instrumenting Bitstreams for Debugging FPGA Circuits

The Multiple Wordlength Paradigm

FPGA Implementation of Pipelined On-Line Scheme for 3-D Vector Normalization

A Reconfigurable Co-Processor for Variable Long Precision Arithmetic Using Indian Algorithms

An Efficient Content-Addressable Memory Implementation Using Dynamic Routing

Lava and JBits: From HDL to Bitstream in Seconds

Architecture and Application of PLATO, A Reconfigurable Active Network Platform

Totem: Custom Reconfigurable Array Generation

A Cellular Automata System with FPGA

A Fault-Tolerance Scheme for a MIN-Based Multi-Sensor System

Column-Based Precompiled Configuration Techniques for FPGA

Configuration Compression for Virtex FPGAs

An 8x8 IDCT Implementation on an FPGA-Augmented TriMedia

Pilchard — a reconfigurable computing platform with memory slot interface

Acceleration of a 2D-FFT on an Adaptable Computing Cluster

Design and Implementation of a Generic 2-D Biorthogonal Discrete Wavelet Transform on an FPGA

An Application-Specific Compiler for High-Speed Binary Image Morphology

One-Step Compilation of Image Processing Applications to FPGAs

High Level Programming for FPGA Based Image and Video Processing Using Hardware Skeletons

Fast Regular Expression Matching Using FPGAs

A Configurable Hardware/Software Approach to SAT Solving

The Development of an Operating System for Reconfigurable Computing

JBits™ Design Abstractions

A Behavioral Synthesis Estimation Interface for Configurable Computing

An Approach for Automatic Data Allocation in C to HDL Compilers

System on a FPGA Virtual Concatenation

Secure Configuration of a Field Programmable Gate Array

Circlets: Circuitry over the Internet

Evaluation of Reconfigurable Cache Module Architecture

An External Memory Interface for FPGA-Based Computing Engines

A SW/HW Interface API for Java/FPGA Co-Designed Applets

The FPGA Development System CHDL

Combining Instruction and Loop Level Parallelism for FPGAs

Mutable Functional Units: Initial Results

Rapid Synthesis of Pattern Classification Circuits

The Effect of FPGA Granularity on Video Codec Implementations

Accelerating Statistical Texture Analysis with an FPGA-DSP Hybrid Architecture

Hardware Implementation of Automated Sensor Self-Validation System for Cupola Furnaces

Reconfigurable Designs for Ray Tracing

Manufacturing Shop-Floor Supercomputer for Distributed Simulation and Control

Pipelined Function Evaluation on FPGAs

Optimization of Logic Use on Stereo Vision Algorithm Example

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)

System on a FPGA Virtual Concatenation

Content Provider	IEEE Xplore Digital Library
Author	Sezer, S. Stewart, E. Carson, M. Greenwood, C.
Copyright Year	2001
Description	Author affiliation: The Queen’s University of Belfast (Sezer, S.)
Abstract	This paper presents the study and implementation of a novel architecture for a virtual concatenation circuit using the NIOS soft core embedded processor on a FPGA (APEX). The architecture is optimised for rapid adaptation of the virtual concatenation core by exploiting the reconfigurable properties of the FPGA technology and the programmable properties of embedded processors. This synergy provides a hardware efficient implementation of hitless re-configuration of transmission paths and the rapid adaptation of the architecture for a wide range of data transmission products to keep pace with product and standard migrations.
Starting Page	257
Ending Page	258
File Size	89029
Page Count	2
File Format	PDF
ISBN	0769526675
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-03-29
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Non IEEE
Subject Keyword	Field programmable gate arrays Synchronous digital hierarchy Telecommunication traffic Circuits Bandwidth Data communication Hardware Concatenated codes Microprogramming Buildings
Content Type	Text
Resource Type	Article

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