NDLI: A new approach for obtaining all logic gates using Chua's circuit with fixed input/output levels

Content Provider	IEEE Xplore Digital Library
Author	Rizk, M.R.M. Nasser, A.A. El-Badawy, E.-S.A. Abou-Bakr, E.
Copyright Year	2012
Description	Author affiliation: ECE Dept, Alexandria Higher Institute of Engineering & Technology (AIET), Egypt (Abou-Bakr, E.) \|\| ECE Dept, College of Eng. and Techno., Arab Academy for Science and Technology (AAST), Alexandria, Egypt (Nasser, A.A.) \|\| EE Dept, Fac. of Engineering, Pharos Univ. and Alexandria Univ., Egypt (El-Badawy, E.-S.A.) \|\| EE Dept, Fac. of Engineering, Alexandria Univ., Egypt (Rizk, M.R.M.)
Abstract	This paper presents a universal logic gate to perform all logic functions, namely, AND, OR, NAND, NOR, and XOR operations without changing the circuit topology. The basic advantage behind our scheme is that there is no need for level conversion between logic levels at the gate terminals (direct hardwiring). The circuit used for verifying the above functions is the Chua's circuit (continuous time domain). VHDL-AMS verification is included to show the validity of the proposed gate.
Starting Page	12
Ending Page	17
File Size	286458
Page Count	6
File Format	PDF
ISBN	9781467304856
e-ISBN	9781467304849
DOI	10.1109/JEC-ECC.2012.6186948
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-03-06
Publisher Place	Egypt
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Chaotic communication Universal logic gate VHDL-AMS Logic gates Time domain analysis Logic functions Chua's circuit Integrated circuit modeling Equations
Content Type	Text
Resource Type	Article

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