NDLI: Modified energy efficient carry save adder

Content Provider	IEEE Xplore Digital Library
Author	Bennet, B. Maflin, S.
Copyright Year	2015
Description	Author affiliation: ETCE Dept., Sathyabama Univ., Chennai, India (Bennet, B.; Maflin, S.)
Abstract	The main aim of the paper is to produce the asynchronous energy efficient of the carry save adder. In the past decade, the VLSI power design constraints have been steadily geared up. The power dissipation is a critical concern in the design of VLSI. The power loss is caused by the leakage current. It was actually ignored in the past but now it consumes half of the total power consumption of modern high level VLSI chips, these power constraints has been very much overcome by the complexities which are shrunk in to the core submicron area, then motionless certain adder has the supreme power degeneracy. The core advantage of the carry save adder is its reduced proliferation interruption, then immobile it aches aimed at the power degeneracy and maximum power leakage which takes place for carry save adder. The control feasting is the highlight of this project and development of compact and efficient high level performance adders. In this presentation, the power consumption is much reduced for the carry save adders, which holds the maximum power dissipation.
Starting Page	1
Ending Page	4
File Size	280798
Page Count	4
File Format	PDF
e-ISBN	9781479970759
DOI	10.1109/ICCPCT.2015.7159503
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Carry save Adder Energy losses and CMOS process Very large scale integration Energy efficiency CMOS integrated circuits Power dissipation Transistors Adders Clocks
Content Type	Text
Resource Type	Article

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