NDLI: Full-custom design and characterization of a phase locked loop

Content Provider	IEEE Xplore Digital Library
Author	Atendido, Kenneth Martin C. Co, Justin Daniel C. Navarro, Jose Gianmarco B. Garcia, Pamela Candice H. Abad, Alexander C.
Copyright Year	2014
Description	Author affiliation: Electronics and Communications Engineering Department Gokongwei College of Engineering De La Salle University Manila, Philippines (Atendido, Kenneth Martin C.; Co, Justin Daniel C.; Navarro, Jose Gianmarco B.; Garcia, Pamela Candice H.; Abad, Alexander C.)
Abstract	The DLS565 is a Phase-locked loop (PLL) Integrated Circuit (IC) design project simulated on all process corner libraries (TT, FF, SS, FS, SF) using 0.5um CMOS technology. The final IC design layout of the PLL without bonding pads covers approximately 0.46mm × 0.5mm. The parameters of the DLS565 were measured and compared to the commercially available LM565C and NE565. It operates with a supply voltage of ±2.5 V with a maximum power dissipation of approximately 22 mW. DLS565 was able to capture frequencies as low as 15Hz and as high as 1.12MHz.
Starting Page	1
Ending Page	6
File Size	412465
Page Count	6
File Format	PDF
e-ISBN	9781479940202
DOI	10.1109/HNICEM.2014.7016240
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-11-12
Publisher Place	Philippines
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lowpass Filter (LPF) Phase Detector (PD) Phase-Locked Loop (PLL) Voltage-controlled oscillators Capacitors Cutoff frequency Layout Detectors Voltage-Controlled Oscillator (VCO) Transistors Phase locked loops
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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