NDLI: Heuristics for greedy transport triggered architecture interconnect exploration

Content Provider	IEEE Xplore Digital Library
Author	Viitanen, T. Kultala, H. Jaaskelainen, P. Takala, J.
Copyright Year	2014
Description	Author affiliation: Dept. of Pervasive Comput., Tampere Univ. of Technol., Tampere, Finland (Viitanen, T.; Kultala, H.; Jaaskelainen, P.; Takala, J.)
Abstract	Most power dissipation in Very Large Instruction Word (VLIW) processors occurs in their large, multi-port register files. Transport Triggered Architecture (TTA) is a VLIW variant whose exposed datapath reduces the need for RF accesses and ports. However, the comparative advantage of TTAs suffers in practice from a wide instruction word and complex interconnection network (IC). We argue that these issues are at least partly due to suboptimal design choices. The design space of possible TTA architectures is very large, and previous automated and ad-hoc design methods often produce inefficient architectures. We propose a reduced design space where efficient TTAs can be generated in a short time using excecution trace-driven greedy exploration. The proposed approach is evaluated by optimizing the equivalent of a 4-issue VLIW architecture. The algorithm finishes quickly and produces a processor with 10% reduced core energy product compared to a fully-connected TTA. Since the generated processor has low IC power and a shorter instruction word than a typical 4-issue VLIW, the results support the hypothesis that these drawbacks of TTA can be worked around with efficient IC design.
Starting Page	1
Ending Page	7
File Size	375147
Page Count	7
File Format	PDF
ISBN	9781450330503
DOI	10.1145/2656106.2656123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-12
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Integrated circuits Radio frequency TTA Program processors Ports (Computers) Computer architecture Port sharing Benchmark testing VLIW Design space exploration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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