NDLI: A low power preamplifier latch based comparator using 180nm CMOS technology

Content Provider	IEEE Xplore Digital Library
Author	Tabassum, S. Bekal, A. Goswami, M.
Copyright Year	2013
Description	Author affiliation: Microelectron. Div., Indian Inst. of Inf. Technol. (IIIT-A), Allahabad, India (Tabassum, S.; Bekal, A.; Goswami, M.)
Abstract	Design of high speed low power comparators are required to build an efficient analog to digital converters (ADCs). This paper mainly focuses on the preamplifier positive feedback latch based comparator for Asynchronous Successive Approximation Register ADC (ASAR ADC). The main components of such comparator are the preamplifier and latch circuit. Preamplifier is used for removing the kickback noise and the dc offset voltage while the latch is required for the comparison. The proposed architecture operates on three phases which are non overlapping and dissipates 70μWpower when operated on a single 1V supply voltage. The latch is basically a back to back connected inverter circuit which is activated only during the second phase. This specialty credits to the least power dissipation in the circuitry which was designed in 180nm CMOS technology.
Sponsorship	IEEE Circuits Syst. Soc.
Starting Page	208
Ending Page	212
File Size	395449
Page Count	5
File Format	PDF
e-ISBN	9781479927517
DOI	10.1109/PrimeAsia.2013.6731207
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analog to digital convertor (ADC) Latches Conferences Asynchronous successive approximation register (ASAR) Preamplifiers Inverters CMOS integrated circuits Microelectronics Transistors
Content Type	Text
Resource Type	Article

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