NDLI: A highly efficient FPGA implementation of AES cryptography

Content Provider	IEEE Xplore Digital Library
Author	Gomes, Otavio S. M. Moreno, Robson L. Pimenta, Tales C.
Copyright Year	2011
Description	Author affiliation: Universidade Federal de Itajubá - UNIFEI, Brazil (Gomes, Otavio S. M.; Moreno, Robson L.; Pimenta, Tales C.)
Abstract	This article describes the core implementation of an Advanced Encryption Standard - AES in Field Programmable Gate Array - FPGA. The core was implemented in both Xilinx Spartan-3 and Xilinx Virtex-5 FPGAs. The algorithm was implemented for 128 bits word and key. The implementation was very efficient, achieving 318MHz on a Xilinx Spartan-3, representing at 50% faster than other reported works. The implementation can achieve 800MHz on a Xilinx Virtex-5. The main goal of this work was the implementation of a fast and modular AES algorithm, as it can be easily reconfigured to 128, 196 or 256 bits key, and can find a wide range of applications. Nevertheless, all the reported works used as comparison basis to our work were also implemented using 128 bits key.
Starting Page	1
Ending Page	4
File Size	654337
Page Count	4
File Format	PDF
ISBN	9781424494842
e-ISBN	9781424494859
DOI	10.1109/LASCAS.2011.5750313
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-23
Publisher Place	Colombia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis DES Efficient encryption/decryption implementation Software algorithms FPGA NIST Hardware Encryption Cryptography Field programmable gate arrays AES
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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