NDLI: A novel low-swing transceiver for interconnection between NoC routers

Content Provider	IEEE Xplore Digital Library
Author	Yi Liu Gang Liu Yintang Yang Zijin Li
Copyright Year	2011
Description	Author affiliation: Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Xi'an, China (Yi Liu; Yintang Yang) \|\| Institute of Microelectronics, Xidian University, Xi'an, China (Gang Liu; Zijin Li)
Abstract	For interconnect between NoC (Network-on-Chip) routers, power consumption is high and data rates are limited when conventional transceivers are used. In this paper, a novel high-speed and low-power source-synchronous transceiver is proposed. An improved low-swing FIR (Finite Impulse Response) filter with resistive pre-emphasis in combination with a double-tail sense amplifier enables a achievable data-rate of 9Gb/s over a 2mm twisted differential interconnect, while consuming only 181fJ/b. By transmitting the clock signals with reduced swing, power consumption of the source-synchronous clock is reduced by 66%.
Starting Page	39
Ending Page	44
File Size	308223
Page Count	6
File Format	PDF
ISBN	9781457704734
e-ISBN	9788988678473
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-16
Publisher Place	Korea (South)
Access Restriction	Subscribed
Rights Holder	AICIT
Subject Keyword	Interconnect Transmitters Source-synchronous Wires Integrated circuit interconnections Pre-emphasis Network-on-Chip (NoC) Finite impulse response filter Transceivers Low-swing Delay Clocks
Content Type	Text
Resource Type	Article

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