NDLI: A BiCMOS technology with 660 MHz vertical PNP transistors for analog/digital ASICs

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2015 IEEE Custom Integrated Circuits Conference (CICC)

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044)

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327)

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Proceedings of CICC 97 - Custom Integrated Circuits Conference

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1992 Proceedings of the IEEE Custom Integrated Circuits Conference

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A special purpose coprocessor supporting cell placement and floorplanning algorithms

A new floorplanning algorithm for analog circuits

A hierarchical floor-planning, placement, and routing tool for sea-of-gates designs

An interior point method for solving the global routing problem

An efficient layer assignment algorithm for gridless switchbox routing

LOGOPT-a multi-level logic synthesis and optimization system

CHARM: a synthesis tool for high-level chip-architecture planning

ACACIA: the CMU analog design system

From analog design description to layout: a new approach to analog silicon compilation

An integrated switched capacitor filter design system

Design automation system for analog circuits based on fuzzy logic

A 6 nsec CMOS EPLD with &mu;W standby power

A function specific EPLD for the PS/2 Micro Channel Bus adapter

The effect of logic block complexity on area of programmable gate arrays

Electrical and geometrical circuit performance using an advanced sea-of-gates philosophy

A gate matrix deformation and three-dimensional maze routing for dense MOS module generation

A 12 ns, CMOS programmable logic device for combinatorial applications

A 7.5 ns 350 mW BiCMOS PAL-type device

A 15 ns 2500 gate highly flexible CHMOS EPLD

A 5000-gate CMOS EPLD with multiple logic and interconnect arrays

An 11 bit, 50 kSample/s CMOS A/D converter cell using a multislope integration technique

An 8-bit two-step flash A/D converter for video applications

CMOS low distortion sample and hold circuit for audio D/A converter

A complete single supply CMOS 12 bit DAC

A 10-bit high speed CMOS CAS macrocell

A 30 MHz low-noise CMOS preamplifier for disk drive heads

A differential PLL architecture for high speed data recovery

CMOS analog front-end for conversational video phone modem

A precision optical metering system for medical instrumentation

A four chip implantable defibrillator/pacemaker chipset

A novel BiMOS switch for use in switched-capacitor filters

BiNMOS: a basic cell for BiCMOS sea-of-gates

A 350 ps 50 K 0.8 &mu;m BiCMOS gate array with shared bipolar cell structure

A 12 bit 5 &mu;sec CMOS recursive ADC with 25 mW power consumption

A high-performance perpendicular FDIC using analog and digital standard cell methodology

A 177 K gate 150 PS CMOS SOG with 1856 I/O buffers

0.8 &mu;m 1.4 MTr. CMOS SOG based on column macro-cell

A 100 K gate sub-micron BiCMOS gate array

A 0.5 &mu;m BiCMOS channelless gate array

Physics-based bipolar transistor model for low-temperature circuit simulation

Steady-state bipolar transistor simulator for the 77 K-300 K temperature range

A simplified approach for quasi-three-dimensional modeling of npn transistors

A technology-independent device modeling program using simulated annealing optimization

An improved I-V model of small geometry MOSFETs for SPICE

A three-transistor model for submicron MOSFET

Simulating the effects of single-event and radiation phenomena on GaAs MESFET integrated circuits

A high density NAND EEPROM with block-page programming for microcomputer applications

A 2 K byte fully-associative cache memory with on-chip DRAM control

A custom processor for use in a parallel computer system

An ECL compatible full CMOS 210 Mbps crosspoint switch

A BiCMOS 32-bit execution unit for 70 MHz VLSI computer

CMOS high speed digital datastrobe processor

Design of an analog 8-bit two-channel I/O ASIC for disk drive control applications

A 16 Mbps adapter chip for the IBM token-ring local area network

An intelligent multiplexer/driver integrated circuit for an implantable multichannel blood flowmeter

A CMOS camera control IC

An integrated digital Y/C separator for S-VHS VCR

A CMOS 100 MHz digital oscilloscope point processor and time base integrated circuit

BLITZEN: a VLSI array processing chip

A four-processor building block for SIMD processor arrays

A high speed data encryption processor for public key cryptography

A VLSI fuzzy logic inference engine for real-time process control

A bit-serial VLSI receptive field accumulator

A synthetic neural integrated circuit

Fully digital neural network implementation based on pulse density modulation

iSPLICE3: a new simulator for mixed analog/digital circuits

A new multi-level timing simulation environment for timing verification

Hierarchical timing view generation including accurate modeling for false paths

An analytical model for BiCMOS logic transient response allowing parameter variations

Analysis of pulse propagation on high-speed VLSI chips

An approach to understanding evaluation of simulation results as an integrated task

Packaging structures utilizing new `pinless' grid array technologies and vacuum well processes to provide enhanced reliability and circuit densities

VLSI performance compensation for off-chip drivers and clock generation

Low dI/dt noise and reflection free CMOS signal driver

A monolithic 50-200 MHz CMOS clock recovery and retiming circuit

High voltage CMOS LCD driver using low voltage CMOS process

4.0 Gb/s NMOS laser driver

4 Gb/s ECL gate masterslice

Design of digital audio input output chip

VLSI architecture for IEEE 802.5 token-ring LAN controller

Mixed design approaches on the semicustom gate forest

High performance clock distribution for CMOS ASICs

Q20D080 analog RAM logic array

0.6-&mu;m 12 K-gate ECL gate array with RAM and ROM

13000 gate ECL compatible GaAs gate array

A 1.4 ns/64 kb RAM with 85 ps/3680 logic gate array

An analog front end chip for V.32 modems

An analog front end for high speed fast turnaround modems

Analog front-end of an ECBM transceiver for ISDN

A single chip S-interface transceiver for public and private ISDN

A codec with on-chip digital echo canceller

A no-trimming SLIC two-chip set with coin telephone signaling facilities

A 400 MHz CMOS packet transmitter-receiver chip

Automatic circuit and layout design for mixed analog/digital ASICs

PROMPT3-a cell-based transistor sizing program using heuristic and simulated annealing algorithms

MOSIZ: a two-step transistor sizing algorithm based on optimal timing assignment method for multi-stage complex gates

Operational amplifier compilation with performance optimization

Optimal ordering of gate signals in CMOS complex gates

Geometric compaction of building-block layout

SDC cell-a novel CMOS/BiCMOS design methodology for mainframe arithmetic module generation

Applications of CVD tungsten in VLSI circuits

A submicron CMOS triple level metal technology for ASIC applications

GaAs MESFET digital integrated circuits fabricated with low temperature buffer technology

A five-volt only flash EEPROM technology for high density memory and system IC applications

A submicron analog CMOS technology

A BiCMOS technology with 660 MHz vertical PNP transistors for analog/digital ASICs

A dual-poly $(n^{+}/p^{+})$ gate, Ti-salicide, double-metal technology for submicron CMOS ASIC and logic applications

The input/output specifications analyzer for IC designs

An approach to knowledge-based ASIC specification

An advanced design system: design capture, functional test generation, mixed level simulation and logic synthesis [VLSI]

Optimized design method for full-custom microprocessors

A fully integrated design methodology for 100 K-gate CMOS custom LSIs with TAB packaging

Computer aids for high performance CMOS custom design

A mask programmable DSP array

A high speed FIR filter designed by compiler

A 20-bit decimator IC for high-resolution audio A/D conversion

The design of DSP components for the CD digital audio system using silicon compilation techniques

A multi-channel digital demodulator for LVDT and RVDT position sensors

RIPAC: a VLSI processor for speech recognition

A VLSI wordprocessing subsystem for a real time large vocabulary continuous speech recognition system

Switched-capacitor simulation models for full-chip verification

Functional-level simulation of switched-capacitor circuits with nonideal switches and operational amplifiers

Dominant pole(s)/zero(s) analysis for analog circuit design

Extending SPICE for electro-thermal simulation

Computing DC large change sensitivities

Statistical sensitivity analysis of MOSFET integrated circuits using process database

A fast multipole algorithm for capacitance extraction of complex 3-D geometries

A self-testing ALU using built-in current sensing

A serial interfacing technique for built-in and external testing of embedded memories

Detecting stuck-open faults with stuck-at test sets

Boundary scan and its application to analog-digital ASIC testing in a board/system environment

Built-in test of CMOS state machines with realistic faults: a system perspective

Physical design of testable VLSI: techniques and experiments

Testing and failure analysis methodology of the NS32532 microprocessor

A compiler for optimized arithmetic datapaths

A datapath multiplier with automatic insertion of pipeline stages

An N-bus datapath compiler for IC design

A 1.0 &mu;m compilable FIFO buffer for standard cell

A generator for high-density macrocells with hierarchical structure

High speed multi-port static RAM silicon compiler

PANDA-a hierarchical mixed mode VLSI module assembler

Modular design of a high performance 32-bit microcontroller

A mixed analog/digital video signal processing LSI with on-chip AD and DA converters

A digital video signal post-processor for color image sensors

A programmable 1400 MOPS video signal processor

A 30 ns (600 MOPS) image processor with a reconfigurable pipeline architecture

The design and implementation of the IMS A110 image and signal processor

A high speed outline front rasterizing LSI

Programmable, four-channel, 128-sample, 40-Ms/s analog-ternary correlator

A 10.7 MHz continuous-time bandpass filter bipolar IC

A very-linear CMOS transconductance stage for OTA-C filters

A 2.4 &mu;m CMOS switched-capacitor video decimator with sampling rate reduction from 40.5 MHz to 13.5 MHz

A rail-to-rail input/output CMOS power amplifier

Construction of analog library cells for analog/digital ASICs using novel design and modular assembly techniques

Design and optimisation of CMOS wideband amplifiers

Built-in self-repair circuit for high-density ASMIC

Limitations of the stuck-at fault model as an accurate measure of CMOS IC quality and a proposed schematic level fault model

Metastability of CMOS latch/flip-flop

An expert system to assist in diagnosis of failures on VLSI memories

Hot carrier effects on CMOS circuit performance

Pulse-width degradation in digital circuits

The QML-an approach for qualifying ASICs

A 15 ns 32&times;32-bit CMOS multiplier with an improved parallel structure

A 3.8 ns CMOS 16&times;16 multiplier using complementary pass transistor logic

A 140 Mb/s CMOS crosspoint chip for switching networks with dynamic path-rearrangement

Design methodologies and CAD tools [VLSI]

Proceedings of the IEEE 1988 Custom Integrated Circuits Conference

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