NDLI: A CMOS 8-bit 20MHz two-step parallel A/D converter with 95mW power consumption

Content Provider	IEEE Xplore Digital Library
Author	Fukushima, N. Kumazawa, N. Soneda, M. Yamada, T.
Copyright Year	1988
Description	Author affiliation: Sony Corp., Kanagawa, Japan (Fukushima, N.; Kumazawa, N.; Soneda, M.; Yamada, T.)
Abstract	The need for a low-cost, high-speed A/D converter with low power consumption is growing as digital video-signal processing applications in the consumer electronics field increase. Although a flash ADC offers a sufficiently high conversion rate for video applications, it has a high power consumption because of its large number of comparators. The two-step parallel ADC, on the other hand, has significantly fewer comparators, and thus a lower power consumption and, because its chip size is smaller, it can be made at lower cost. A conventional two-step parallel ADC has, however, three problems: a relatively slow conversion rate, a relatively poor differential linearity, and the need for a peripheral sample-and-hold circuit. The authors report a new 8-bit two-step parallel ADC which solves these problems.<>
Starting Page	238
Ending Page	239
File Size	116219
Page Count	2
File Format	PDF
DOI	10.1109/ICCE.1988.10778
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-06-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy consumption Voltage Circuits CMOS process Linearity Pipeline processing Error correction Switches Timing Latches
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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