NDLI: A zero-skew clock routing scheme for VLSI circuits

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2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

1992 IEEE/ACM International Conference on Computer-Aided Design

Hazard-non-increasing gate-level optimization algorithms

Exact two-level minimization of hazard-free logic with multiple-input changes

A comparative study of design for testability methods using high-level and gate-level descriptions

Behavioral synthesis for easy testability in data path scheduling

Behavioral synthesis for testability

Area minimization for general floorplans

Three-phase chip planning-an improved top-down chip planning strategy

Accurate net models for placement improvement by network flow methods

SHILPA: a high-level synthesis system for self-timed circuits

Automatic gate-level synthesis of speed-independent circuits

Automatic synthesis of 3D asynchronous state machines

COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits

An efficient non-enumerative method to estimate path delay fault coverage

Test generation for delay faults in non-scan and partial scan sequential circuits

DAMOCLES: an observer-based approach to design tracking

Incorporating design flow management in a framework based CAD system

DECOR-tightly integrated design control and observation

Precise timing verification of logic circuits under combined delay model

Valid clocking in wavepipelined circuits

Exploiting multi-cycle false paths in the performance optimization of sequential circuits

Performance optimization of sequential circuits by eliminating retiming bottlenecks

Assignment of global memory elements for multi-process VHDL specifications

Synthesis of the hardware/software interface in microcontroller-based systems

A partitioning algorithm for system-level synthesis

Design of system interface modules

Perfect-balance planar clock routing with minimal path-length

HERO: Hierarchical EMC-constrained routing

Zero skew clock routing in multiple-clock synchronous systems

A zero-skew clock routing scheme for VLSI circuits

Time domain analysis of nonuniform frequency dependent high-speed interconnects

An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines

Efficient techniques for inductance extraction of complex 3-D geometries

Optimal replication for min-cut partitioning

A probabilistic multicommodity-flow solution to circuit clustering problems

A new approach to effective circuit clustering

A new algorithm for the binate covering problem and its application to the minimization of Boolean relations

ProperSYN: A portable parallel algorithm for logic synthesis

Efficient Boolean function matching

On average power dissipation and random pattern testability of CMOS combinational logic networks

System-level routing of mixed-signal ASICs in WREN

A wire-length minimization algorithm for single-layer layouts

Detailed layer assignment for MCM routing

Maze router without a grid map

A logic simulation engine based on a modified data flow architecture

Reconfigurable machine and its application to logic diagnosis

Parallel logic and fault simulation algorithms for shared memory vector machines

Ravel: assinged-delay compiled-code logic simulation

Accurate layout area and delay modeling for system level design

Timing analysis in high-level synthesis

False loops through resource sharing (logic CAD)

FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databases

Equivalent design representations and transformations for interactive scheduling

An efficient multi-view design model for real-time interactive synthesis

Behavioral simulation for noise in mixed-mode samples-data systems

Accurate simplification of large symbolic formulae

Lazy-expansion symbolic expression approximation in SYNAP

Maximally fast and arbitrarily fast implementation of linear computations (circuit layout CAD)

HYPER-LP: a system for power minimization using architectural transformations

Area optimization of multi-functional processing units

Efficiency improvements for force-directed scheduling

Efficient partitioning and analysis of digital CMOS-circuits

On the generation of small dictionaries for fault location

E-PROOFS: A CMOS bridging fault simulator

An optimal probe testing algorithm for the connectivity verification of MCM substrates

ETA: electrical-level timing analysis

A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling

Analytic macromodeling and simulation of tightly-coupled mixed analog-digital circuits

Optimal synthesis of multichip architectures

A scheduling method by stepwise expansion in high-level synthesis

An effective methodology for functional pipelining

Automatic test generation for linear digital systems with bi-level search using matrix transform methods

Portable parallel test generation for sequential circuits

CRIS: A test cultivation program for sequential VLSI circuits

A probabilistic timing approach to hot-carrier effect estimation

Power estimation tool for sub-micron CMOS VLSI circuits

Delay and bus current evaluation in CMOS logic circuits

Verification of asynchronous interface circuits with bounded wire delays

Automatic generation and verification of sufficient correctness properties for synchronous processors

Verification of systems containing counters

Automatic compositional minimization in CTL model checking

Automatic differentiation in circuit simulation and device modeling

MOSAIC: a tile-based datapath layout generator

An optimal chip compaction method based on shortest path algorithm with automatic jog insertion

Cloning techniques for hierarchical compaction

HIMALAYAS-A hierarchical compaction system with a minimized constraint set

Using constraint geometry to determine maximum rate pipeline clocking

Identification of critical paths in circuits with level-sensitive latches

Verifying clock schedules

On the verification of state-coding in STGs

A generalized state assignment theory for transformations on signal transition graphs

A unified signal transition graph model for asynchronous control circuit synthesis

Exhaustive simulation need not require an exponential number of tests

McPOWER: a Monte Carlo approach to power estimation

Timing distribution in VHDL behavioral models

Numerical integration algorithms and asymptotic waveform evaluation (AWE)

Extension of the asymptotic waveform evaluation technique with the method of characteristics

AWE macromodels of VLSI interconnect for circuit simulation

Rectification method for lookup-table type FPGA's

An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs

A tutorial on logic synthesis for lookup-table based FPGAs

Aesthetic routing for transistor schematics

Graph algorithms for clock schedule optimization

VLSI design parsing

On channel segmentation design for row-based FPGAs

New channel segmentation model and associated routing algorithm for high performance FPGAs

An algorithm to reduce test application time in full scan designs

Configuration of boundary scan chain for optimal testing of clusters of non boundary scan devices

Overall consideration of scan design and test generation

Configuring multiple scan chains for minimum test time

1992 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.92CH03183-1)

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

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