NDLI: Fast cycle-accurate behavioral simulation for pipelined processors using early pipeline evaluation

Content Provider	IEEE Xplore Digital Library
Author	In-Cheol Park Sehyeon Kang Yongseok Yi
Copyright Year	2003
Description	Author affiliation: KAIST, Daejeon, South Korea (In-Cheol Park; Sehyeon Kang; Yongseok Yi)
Abstract	Modeling and simulating pipelined processors in procedural languages such as C/C++ requires lots of cost in handling concurrent events, which hinders fast simulation. A number of researches on simulation have devised speed-up techniques to reduce the number of events. This paper presents a new simulation approach developed to enhance the simulation of pipelined processors. The proposed approach is based on early pipeline evaluation that all the intermediate values of an instruction are computed in advance, creating a future state for the next instructions. The future state allows the next instructions to be computed without considering data dependencies between nearby instructions. We apply this concept to building a cycle-accurate simulator for a pipelined RISC processor and achieve almost the same speed as the instruction-level simulator.
Sponsorship	IEEE IEEE Circuits and Syst. Soc. IEEE Comput. Soc. ACM Special Interest Group on Design Automation
Starting Page	138
Ending Page	141
File Size	370331
Page Count	4
File Format	PDF
ISBN	1581137621
DOI	10.1109/ICCAD.2003.159682
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Pipelines Object oriented modeling Computational modeling Hardware Timing Discrete event simulation Accuracy Hazards Delay Computer aided instruction
Content Type	Text
Resource Type	Article

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