NDLI: Power invariant vector sequence compaction

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2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers

2008 IEEE/ACM International Conference on Computer-Aided Design

2007 IEEE/ACM International Conference on Computer-Aided Design

2006 IEEE/ACM International Conference on Computer Aided Design

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005.

IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002.

IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281)

IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287)

1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers [Front Matter and Table of Contents]

Tutorial 2 Real-time Operating Systems For Embedded Computing

Tutorial I Embedded Memories In System Design From Technology To Systems Architecture

Tutorial 3 High-level Design Validation And Test

Tutorial 4 Interconnect In High Speed Designs: Problems, Methodologies And Tools

Panel: How will Cad Handle Billion-transistor Systems?

Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress

Simulation of coupling capacitances using matrix partitioning

h-gamma: an RC delay metric based on a gamma distribution approximation of the homogeneous response

Wireplanning in logic synthesis

Graph matching-based algorithms for FPGA segmentation design

Delay-oriented technology mapping for heterogeneous FPGAs with bounded resources

Control generation for embedded systems based on composition of modal processes

Representation of process mode correlation for scheduling

CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems

Synthesis of BIST hardware for performance testing of MCM interconnections

Using a single input to support multiple scan chains

High-level variable selection for partial-scan implementation

Multipoint moment matching model for multiport distributed interconnect networks

Reduced-order modelling of linear time-varying systems

Model reduction of time-varying linear systems using approximate multipoint Krylov-subspace projectors

Implementation and use of SPFDs in optimizing Boolean networks

Finding all simple disjunctive decompositions using irredundant sum-of-products forms

On accelerating pattern matching for technology mapping

A performance-driven layer assignment algorithm for multiple interconnect trees

Optimal 2-D cell layout with integrated transistor folding

Integrating logic retiming and register placement

Static compaction using overlapped restoration and segment pruning

Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits

A fast, accurate, and non-statistical method for fault coverage estimation

Simulation of high-Q oscillators

Phase noise in oscillators: DAEs and colored noise sources

High-order Nystrom schemes for efficient 3-D capacitance extraction

Signature hiding techniques for FPGA intellectual property protection

Analysis of watermarking techniques for graph coloring problem

Intellectual property protection by watermarking combinational logic synthesis solutions

Estimating noise in RF systems

Getting to the bottom of deep submicron

Determination of worst-case aggressor alignment for delay calculation

Noise considerations in circuit optimization

Energy-efficiency in presence of deep submicron noise

Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

Domino logic synthesis using complex static gates

Technology mapping for domino logic

Slicing floorplans with pre-placed modules

Arbitrary rectilinear block packing based on sequence pair

The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear blocks

On primitive fault test generation in non-scan sequential circuits

Test set compaction algorithms for combinational circuits

A linear optimal test generation algorithm for interconnect testing

GPCAD: a tool for CMOS op-amp synthesis

An efficient DC root solving algorithm with guaranteed convergence for analog integrated CMOS circuits

Efficient analog circuit synthesis with simultaneous yield and robustness optimization

Reencoding for cycle-time minimization under fixed encoding length

Using precomputation in architecture and logic resynthesis

Lazy transition systems: application to timing optimization of asynchronous circuits

A general approach for regularity extraction in datapath circuits

SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C

A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis

Approximate Reachability Don't Cares for CTL model checking

Adaptive variable reordering for symbolic model checking

Verification by approximate forward and backward reachability

CMOS analog circuit stack generation with matching constraints

Testability analysis and multi-frequency ATPG for analog circuits and systems

CONCERT: a concurrent transient fault simulator for nonlinear analog circuits

Waiting false path analysis of sequential logic circuits for performance optimization

Asymptotically efficient retiming under setup and hold constraints

On the optimization power of retiming and resynthesis transformations

Architecture driven circuit partitioning

Integrating floorplanning in data-transfer based high-level synthesis

The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications

A graph-partitioning-based approach for multi-layer Constrained Via Minimization

Hardware/software co-synthesis with memory hierarchies

Communication synthesis for distributed embedded systems

Analysis of emerging core-based design lifecycle

Core integration: overview and challenges

Full-chip verification of UDSM designs

Node sampling: a robust RTL power modeling approach

Estimation of power sensitivity in sequential circuits with power macromodeling application

Power invariant vector sequence compaction

Efficient encoding for exact symbolic automata-based scheduling

A new algorithm for the reduction of incompletely specified finite state machines

Static power optimization of deep submicron CMOS circuits for dual V/sub T/ technology

Network flow based circuit partitioning for time-multiplexed FPGAs

On multilevel circuit partitioning

Multiway partitioning with pairwise movement

Verification of RTL generated from scheduled behavior in a high-level synthesis flow

Functional debugging of systems-on-chip

Formal verification of pipeline control using controlled token nets and abstract interpretation

Proposal of a timing model for CMOS logic gates driving a CRC /spl pi/ load

Gate-size selection for standard cell libraries

Fanout optimization under a submicron transistor-level delay model

Efficient equivalence checking of multi-phase designs using retiming

Robust latch mapping for combinational equivalence checking

Tight integration of combinational verification methods

Removal of memory access bottlenecks for scheduling control-flow intensive behavioral descriptions

Period assignment in multidimensional periodic scheduling

Improving the computational performance of ILP-based problems

Techniques for energy minimization of communication pipelines

PowerDrive: a fast, canonical POWER estimator for DRIVing synthEsis

Accurate calculation of bit-level transition activity using word-level statistics and entropy function

Shaping a VLSI wire to minimize delay using transmission line model

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

A simultaneous routing tree construction and fanout optimization algorithm

Sampling schemes for computing OBDD variable orderings

The design of a cache-friendly BDD library

Design of experiments in BDD variable ordering: lessons learned

On-line scheduling of hard real-time tasks on variable voltage processor

Transforming control-flow intensive designs to facilitate power management

Synthesis of application specific instructions for embedded DSP software

Word-level decision diagrams, WLCDs and division

Polynomial methods for component matching and verification

Symbolic model checking of process networks using interval diagram techniques

1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

Proceedings of International Conference on Computer Aided Design

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD)

IEEE/ACM International Conference on Computer-Aided Design

Proceedings of 1993 International Conference on Computer Aided Design (ICCAD)

1992 IEEE/ACM International Conference on Computer-Aided Design

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

[1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers

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