NDLI: An 800 MHz 0.35 /spl mu/m CMOS clock tree and PLL based on a new charge-pump circuit

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An 800 MHz 0.35 /spl mu/m CMOS clock tree and PLL based on a new charge-pump circuit

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Proceedings of Third International Conference on Electronics, Circuits, and Systems

An 800 MHz 0.35 /spl mu/m CMOS clock tree and PLL based on a new charge-pump circuit

Content Provider	IEEE Xplore Digital Library
Author	Orcioni, S. Conti, M. Turchetti, C. Centorame, A.
Copyright Year	2002
Description	Author affiliation: Dipt. di Elettronica e Autom., Ancona Univ., Italy (Orcioni, S.; Conti, M.; Turchetti, C.; Centorame, A.)
Abstract	The paper presents the design of an 800 MHz PLL implemented in a 0.35 /spl mu/m CMOS technology. A novel charge pump circuit has been introduced in order to increase the frequency range of the PLL. A clock tree with buffers in the internal nodes has been designed for a chip of dimensions 1 cm/spl times/1 cm. The PLL supports internal to external clock frequency ratios of 1, 2, 4 and 8. PLL and clock tree have been used for power reduction by clock domain partitioning.
Sponsorship	IEEE CAS Soc. IEEE Region 8
Starting Page	571
Ending Page	574
File Size	401378
Page Count	4
File Format	PDF
ISBN	0780375963
DOI	10.1109/ICECS.2002.1046230
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-15
Publisher Place	Croatia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Phase locked loops Charge pumps Circuits CMOS technology Voltage-controlled oscillators Signal generators Energy consumption Frequency conversion Phase detection
Content Type	Text
Resource Type	Article

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