NDLI: Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFETs

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IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest.

Plenary session

Welcome from the General Chair

IEDM Executive Committee

Conference highlights

Plenary session

More than Moore: micro-machined products enable new applications and open new markets

Scaling, power, and the future of CMOS

Past and future technologies of information displays

Process technology high-k i: metal gate stacks

A thermally-stable sub-0.9nm EOT TaSix/HfSiON gate stack with high electron mobility, suitable for gate-first fabrciation of hp45 LOP devices

Advanced MOSFETs using HfTaON/SiO/sub 2/ gate dielectric and TaN metal gate with excellent performances for low standby power application

High performance tantalum carbide metal gate stacks for nMOSFET application

Microstructure modified HfO/sub 2/ using Zr addition with Ta/sub x/ C/sub y/ gate for improved device performance and reliability

Universal theory of workfunctions at metal/Hf-based high-k dielectrics interfaces - guiding principles for gate metal selection

Dependence of pmos metal work functions on surface conditions of high-k gate dielectrics

Integrated circuits and manufacturing advanced cmos and platform technology

Lithography for manufacturing of sub-65nm nodes and beyond

45-nm node CMOS integration with a novel STI structure and full-NCS/Cu interlayers for low-operation-power (lop) applications

High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL

A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

65nm cmos technology for low power applications

System LSI multi-vth transistors design methodology for maximizing efficiency of body-biasing control to reduce vth variation and power consumption

Application of on-chip MIM decoupling capacitor for 90nm SOI microprocessor

Process technology advanced interconnect technology

A robust 45 nm-node, dual damascene interconnects with high quality cu/barrier interface by a novel oxygen absorption process

High performance k=2.5 ULK backend solution using an improved TFHM architecture, extendible to the 45nm technology node

Integration of Cu and extra low-k dielectric (k=2.5/spl sim/2.2) for 65/45/32nm generations

Interconnect issues post 45nm

Advanced scalable ultralow-k/Cu interconnect technology for 32 nm CMOS ULSI using self-assembled porous silica and self-aligned CoWP barrier

Detectors, sensors, and mems organic and flexible electronics

A flexible, lightweight Braille sheet display with plastic actuators driven by an organic field-effect transistor active matrix

Thin film transistor circuits integrated onto elastomeric substrates for elastically stretchable electronics

High mobility solution-processed OTFTs

Low-voltage inkjetted organic transistors for printed RFID and display applications

Realization of a 5-stage divider circuitry in p-type polymer transistor technology

High performance nanocrystalline-Si TFT fabricated at 150/spl deg/ C using ICP-CVD

An integrated position-sensing system for a MEMS-based cochlear implant

RFCPUs on glass and plastic substrates fabricated by TFT transfer technology

CMOS devices mobility enhancement and low resistance source/drain

Physical mechanisms of electron mobility enhancement in uniaxial stressed MOSFETs and impact of uniaxial stress engineering in ballistic regime

New findings on inversion-layer mobility in highly doped channel Si MOSFETs

Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS

Channel backscattering characteristics of strained PMOSFETs with embedded SiGe source/drain

Improved sub-10-nm CMOS devices with elevated source/drain extensions by tunneling si-selective-epitaxial-growth

An integrated methodology for accurate extraction of S/D series resistance components in nanoscale MOSFETs

Solid state and nanoelectronic devices non-volatile memory technologies: MONOS and nanocrystal memories

20nm gate bulk-finFET SONOS flash

Low voltage high speed SiO/sub 2/AlGaN/AlLaO/sub 3/TaN memory with good retention

Long retention and low voltage operation using IrO/sub 2/HfAlO/HfSiO/HfalO gate stack for memory application

High density silicon nanocrystal embedded in sin prepared by low energy (<500eV) SiH/sub 4/ plasma immersion ion implantation for non-volatile memory applications

Enhancement of memory window in short channel non-volatile memory devices using double layer tungsten nanocrystals

Nanocrystal flash memory fabricated with protein-mediated assembly

CMOS and interconnect reliability interconnect, plasma damage, and ESD reliability

Novel dielectric slots in Cu interconnects for suppressing stress-induced void failure

Mechanism of moisture uptake induced via failure and its impact on 45nm node interconnect design

Stress-induced voiding under vias connected to "narrow" copper lines

Process damages in HfO/sub 2//TiN stacks: the key role of H/sup 0/ and H/sub 2/ anneals

New physical insight and modeling of second breakdown (It/sub 2/) phenomenon in advanced esd protection devices

Modeling and simulation compact models

A new compact model for junctions in advanced CMOS technologies

High performance, sub-50nm MOSFETS for mixed signal applications

High-voltage LDMOS compact model for RF applications

Physics-based noise modelling of semiconductor devices in largesignal operation including low-frequency noise conversion effects

CMOS devices high performance CMOS

High performance 35nm L/sub GATE/ CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2nm gate oxide

45-nm node NiSi FUSI on nitrided oxide bulk CMOS fabricated by a novel integration process

High performance cmos bulk technology using direct silicon bond (dsb) mixed crystal orientation substrates

High performance CMOSFET technology for 45nm generation and scalability of stress-induced mobility enhancement technique

Integration and optimization of embedded-sige, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies

High performance 30 nm gate bulk CMOS for 45 nm node with /spl Sigma/-shaped SiGe-SD

Record RF performance of sub-46 nm L/sub gate/ NFETs in microprocessor SOI CMOS technologies

An advanced low power, high performance, strained channel 65nm technology

Solid-state and nanoelectronic devices nanotubes and nanowires for thermal and electrical applications

Carbon nanotube interconnects: implications for performance, power dissipation and thermal management

Electro-thermal transport in metallic single-wall carbon nanotubes for interconnect applications

Thermal and source bumps utilizing carbon nanotubes for flip-chip high power amplifiers

Nanoelectromechanical DRAM for ultra-large-scale integration (ULSI)

Wrap-gated inas nanowire field-effect transistor

A new logic family based on hybrid MOSFET-polysilicon nanowires

Detectors, sensors, and MEMS - MEMS technologies and applications

CMOS-MEMS resonant mixer-filters

Low phase noise array-composite micromechanical wine-glass disk oscillator

Frequency tolerance of RF micromechanical disk resonators in polysilicon and nanocrystalline diamond structural materials

Non-linearity cancellation in MEMS resonators for improved power-handling

Embedded MEMS filter chip and its fabrication for VHF applications

Piezoelectric RF MEMS tunable capacitor with 3V operation using CMOS compatible materials and process

GaN on patterned silicon (GPS) technique for GaN-based integrated microsensors

PECVD-oxynitride gas chromatographic columns

Integrated circuits and manufacturing DRAM and NAND flash

A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM

A novel capacitor-less DRAM cell using thin capacitively-coupled thyristor (TCCT)

Local-damascene-finFET DRAM integration with p/sup +/ doped poly-silicon gate technology for sub-60nm device generations

Overcoming DRAM scaling limitations by employing straight recessed channel array transistors with <100> uni-axial and [100] uni-plane channels

Technology for sub-50nm DRAM and NAND flash manufacturing

A novel NAND-type MONOS memory using 63nm process technology for multi-gigabit flash EEPROMs

A novel p-channel NAND-type flash memory with 2-bit/cell operation and high programming throughput (> 20 MB/sec)

Process technology advanced integration concepts

Challenges for the DRAM cell scaling to 40nm

Fabrication of 3D trench PZT capacitors for 256Mbit FRAM device application

Highly scalable flash memory with novel deep trench isolation embedded into highperformance cmos for the 90nm node & beyond

New three-dimensional integration technology using self-assembly technique

Enabling SOI-based assembly technology for three-dimensional (3d) integrated circuits (ICs)

Self-assembling resists for nanolithography

Quantum, power, and compound semiconductor devices high performance si-rf power and power-switching devices

High frequency power LDMOS technologies for base station applications status, potential, and benchmarking

High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure

Performance and limitations of 65 nm CMOS for integrated RF power applications

Dielectric resurf: breakdown voltage control by STI layout in standard CMOS

AlGaN/GaN devices for future power switching systems

A low on-resistance high voltage soi ligbt with oxide trench in drift region and hole bypass gate configuration

An AlGaN/GaN push-pull HEMT amplifier with 400 MHz bandwidth and 100 W peak output power

CMOS and interconnect reliability gate dielectric breakdown - modeling and mechanism

Mechanisms of hydrogen release in the breakdown of SiO/sub 2/-based gate oxides

The roles of hydrogen and holes in trap generation and breakdown in ultra-thin SiON dielectrics

A comprehensive investigation of gate oxide breakdown of P+Poly/PFETs under inversion mode

Theory of hydrogen-related levels in semiconductors and oxides

Theory of "current-ratio" method for oxide reliability: proposal and validation of a new class two-dimensional breakdown-spot characterization techniques

Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress

Process technology high-k ii: gate dielectrics

Fluorine incorporation into HfSiON dielectric for V/sub th/ control and its impact on reliability for poly-Si gate pFET

Improvement in high-k (HfO/sub 2//SiO/sub 2/) reliability by incorporation of fluorine

Experimental clarification of mobility determining factors in HfSiON CMISFET with various film compositions

High performance gate first HfSiON dielectric satisfying 45nm node requirements

Dramatic improvement of Ge p-MOSFET characteristics realized by amorphous zr-silicate/ge gate stack with excellent structural stability through process temperatures

Ultra-thin (EOT=3/spl Aring/) and low leakage dielectrics of La-alminate directly on si substrate fabricated by high temperature deposition

Emerging technologies flexible electronics

Organic thin film electronics

Flexible, large-area sensors and actuators with organic transistor integrated circuits

Organic circuits on flexible substrates

Organic and hybrid organic/inorganic transistors for chemical and bio sensing

Materials and patterning techniques for macroelectronics

Solid-state and nanoelectronic devices novel device concepts

A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram

A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics

Single molecular devices with fullerenes and oligophenylenevinylene (opv) derivatives

The micro to nano addressing block (MNAB)

Three terminal solid-electrolyte nanometer switch

Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor

Multi-electrode arrays (MEAs) with guided network for cell-to-cell communication transduction

Nanoparticle manipulator by a novel designed MEMS based reactor for physical antibiotics

CMOS devices strained-silicon technology

Design of high performance PFETs with strained si channel and laser anneal

Source/drain germanium condensation for p-channel strained ultra-thin body transistors

Thin body silicon-on-insulator N-MOSFET with silicon-carbon source/drain regions for performance enhancement

New stress inducing technique of epitaxial si on recessed S/D fabricated in substrate strained-si of [100]channel on rotated wafers

Stress memorization in high-performance FDSOI devices with ultra-thin silicon channels and 25nm gate lengths

Uniaxial-biaxial stress hybridization for super-critical strained-si directly on insulator (SC-SSOI) PMOS with different channel orientations.

Dislocation engineering in strained mos materials

Modeling and simulation nanowires and nanotubes

Computational study of carbon nanotube p-i-n tunnel FETs

Performance of carbon nanotube field effect transistors with doped source and drain extensions and arbitrary geometry

Ballistic transport in Si, Ge, and GaAs nanowire MOSFETs

Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs

Performance assessment of sub-percolating nanobundle network transistors by an analytical model

CMOS and interconnect reliability process and electrical degradation in flash memories and performance boosted CMOS devices

4-bit per cell NROM reliability

A new charge-trapping technique to extract SILC-trap time constants in SiO/sub 2/

BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability

Highly reliable 2-bit/cell nitride trapping flash memory using a novel array-nitride-sealing (ANS) ONO process

BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric

A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering

Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFETs

Quantum, power, and compound semiconductor devices gan high-power devices, pushing the limits

A 36mm GaN-on-Si HFET producing 368W at 60V with 70% drain efficiency

An over 100 W n-GaN/n-AlGaN/GaN MIS-HEMT power amplifier for wireless base station applications

Novel AlGaN/GaN dual-field-plate FET with high gain, increased linearity and stability

High power, high AlGaN/GaN-HEMTs with novel powerbar design

8-watt GaN HEMTs at millimeter-wave frequencies

380v/1.9A GaN power-HEMT: current collapse phenomena under high applied voltage and demonstration of 27.1 MHz class-E amplifier

Evidence of traps creation in GaN/AlGaN/GaN HEMTs after a 3000 hour on-state and off-state hot-electron stress

Semiconductor research and development: who will do it and who will pay for it in 2010?

Evening panel discussion will non-volatile memory scale past the end of the decade?

Modeling and simulation transport in advanced planar cmos devices

First-principles modeling of double-gate UTSOI MOSFETs

Novel channel materials for ballistic nanoscale MOSFETs-bandstructure effects

Investigation of the performance limits of III-V double-gate n-MOSFETs

Scaling the high-performance double-gate SOI MOSFET down to the 32 nm technology node with SiO/sub 2/-based gate stacks

A study of the effect of the interface roughness on a DG-MOSFET using a full 2D NEGF technique

Multi-subband monte carlo modeling of nano-mosfets with strong vertical quantization and electron gas degeneration

Process technology fully-silicided gates

Physical mechanism of work function modulation due to impurity pileup at Ni-FUSI/SiO(N) interface

An easily integrable NiSi TOSI-gate/SiON-module for LP SRAM applications based on a single step silicidation of gate and junction

Modulation of the Ni FUSI workfunction by Yb doping: from midgap to n-type band-edge

Lanthanide and Ir-based dual metal-gate/HfAlON CMOS with large work-function difference

Demonstration of Ni fully germanosilicide as a pFET gate electrode candidate on HfSiON

Systematic study of work function engineering and scavenging effect using NiSi alloy FUSI metal gates with advanced gate stacks

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

Ni/sub x/Ta/sub 1-x/Si and Ni/sub x/Pt/sub 1-x/Si ternary alloys for work function tuning on SiO/sub 2/, HfSiO/sub x/ and HfO/sub 2/ dielectrics

Integrated circuits and manufacturing advanced sram and novel integration

Erratic fluctuations of sram cache vmin at the 90nm process technology node

Fluctuation limits & scaling opportunities for CMOS SRAM cells

High density and high speed SRAM bit-cells and ring oscillators due to laser annealing for 45nm bulk CMOS

Ultra-fast programming of silicided polysilicon fuses based on new insights in the programming physics

Wafer-level compliant bump for three-dimensional LSI with high-density area bump connections

Successful transferring of active transistors, rf-passive components and high density interconnect from bulk si to organic substrates

Fabrication and characterization of CMOSFETs on porous silicon for novel device layer transfer

CMOS and interconnect reliability bias-temperature instability and interface traps

On the dispersive versus arrhenius temperature activation of nbti time evolution in plasma nitrided gate oxides: measurements, theory, and implications

Material dependence of hydrogen diffusion: implications for NBTI degradation

Negative bias temperature instability of carrier-transport enhanced pMOSFET with performance boosters

Defect passivation with fluorine in a Ta/sub x/C/ high-K gate stack for enhanced device threshold voltage stability and performance

Accurate circuit performance prediction model and lifetime prediction method of nbt stressed devices for highly reliable ulsi circuits

On-chip charge pumping method for characterization of interface states of ultra thin gate oxide in nano CMOS technology

CMOS devices SOI and multi-gate devices

High performance multi-gate pMOSFET using uniaxially-strained SGOI channels

Inverted T channel FET (ITFET) - Fabrication and characteristics of vertical-horizontal, thin body, multi-gate, multi-orientation devices, ITFET SRAM bit-cell operation. A novel technology for 45nm and beyond CMOS.

High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

GIDL (gate-induced drain leakage) and parasitic schottky barrier leakage elimination in aggressively scaled HfO/sub 2/TiN FinFET devices

Mobility enhancement due to volume inversion in [110]-oriented ultra-thin body double-gate nMOSFETs with body thickness less than 5 nm

Selective epitaxial channel ground plane thin SOI CMOS devices

Solid-state and nanoelectronic devices resistive switching memories

Oxygen-doped gesbte phase-change memory cells featuring 1.5 V/100-/spl mu/A standard 0.13/spl mu/m CMOS operations

Impact of crystallization statistics on data retention for phase change memories

Non-volatile resistive switching for advanced memory applications

Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application

Conductive bridging RAM (CBRAM): an emerging non-volatile memory technology scalable to sub 20nm

Excellent resistance switching characteristics of Pt/SrTiO/sub 3/ schottky junction for multi-bit nonvolatile memory application

Quantum, power and compound semiconductor devices high-speed compound semiconductor devices for logic and communications

85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications

Performance evaluation of 50 nm In/sub 0.7/Ga/sub 0.3/As HEMTs for beyond-CMOS logic applications

Monolithic integration of enhancement-and depletion-mode AlGaN/GaN HEMTs for GaN digital integrated circuits

Laterally scaled down tiered-edge ohmic structure of InP-based HEMTs for 2-S/mmg/sub m/ and 500-GHz f/sub T/

The InP/GaAsSb type-H heterostructure system and its application to high-speed DHBTs and photodetectors: physics, surprises, and opportunities (INVITED)

Non-uniform degradation behavior across device width in RF power GaAs PHEMTs

Ge-spacer technology in AlGaN/GaN HEMTs for mm-wave applications

Detectors, sensors, and MEMS image sensors and photon detection

A high-performance and low-noise CMOS image sensor with an expanding photodiode under the isolation oxide

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

High-speed blue-, red-, and infrared-sensitive photodiode integrated in a 0.35 /spl mu/m SiGe:C-BiCMOS process

A 28 mega pixel large area full frame CCD with 2/spl times/2 on-chip RGB charge-binning for professional digital still imaging

Influence of terrestrial cosmic rays on the reliability of CCD image sensors

On-chip detection and counting of single-photons

An intra-chip electro-optical channel based on CMOS single photon detectors

Process technology advanced FEOL technology

A simple approach to optimizing ultra-thin SiON gate dielectrics independently for n- and p-MOSFETs

Dramatic improvement of V/sub fb/, shift and G/sub m//sup max/ with ultra-thin and ultra-low-leakage SiN-based SiON gate dielectrics

Interface states as an active component for 20 nm gate-length planar MOSFET with electrostatic channel extension (ESCE)

Single stress liner for both NMOS and PMOS current enhancement by a novel ultimate spacer process

Damage-free neutral beam etching technology for high mobility FinFETs

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

Integrated circuits and manufacturing non-volatile memories

A 65nm NOR flash technology with 0.042/spl mu/m/sup 2/ cell size for high performance multilevel application

35 nm floating gate planar MOSFET memory using double junction tunneling

Experimental and theoretical analysis of scaling issues in dual-bit discrete trap non-volatile memories

Robust multi-bit programmable flash memory using a resonant tunnel barrier

Novel transition layer engineered Si nanocrystal flash memory with MHSOS structure featuring large V/sub th/ window and fast P/E speed

Quality assured mass productive 1.6V operational 0.18 /spl mu/m 1T1C FRAM embedded smart card with advanced integration technologies against defectives

High speed toggle MRAM with mgO-based tunnel junctions

Assessment of threshold switching dynamics in phase-change chalcogenide memories

CMOS devices advanced gate stacks

HfSiON-CMOSFET technology for low standby power application

Demonstration of recessed SiGe S/D and inserted metal gate on HfO/sub 2/ for high performance pFETs.

High performance nMOSFET with HfSi/subx//HfO/sub 2/ gate stack by low temperature process

Direct measurement of carrier profiles in operating sub-30-nm N-MOSFETs

Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs

Drive current enhancement in high-K/metal gate germanium-carbide pMOSFETs fabricated directly on Si substrates

Vth-tunable CMIS platform with high-k gate dielectrics and variability effect for 45nm node

Detectors, sensors, and mems thin film transistors for displays and system on panel

0.1/spl mu/m poly-Si thin film transistors for system-on-panel (SoP) applications

High mobility n-channel and p-channel nanocrystalline silicon thin-film transistors

High performance single grain si tfts inside a location-controlled grain by /spl mu/-czochralski process with capping layer

Low temperature single grain thin film transistor (LTSG-TFT) with SOI performance using cmp-flattened /spl mu/-czochralski process

2-bit poly-Si-TFT nonvolatile memory using hafnium oxide, hafnium silicate and zirconium silicate

Highly efficient current scaling AMOLED panel employing a new current mirror pixel circuit fabricated by excimer laser annealed poly-Si TFTs

Novel solid-state spatial light modulator on integrated circuits for high-speed application with electro-optic thin film

100 MHz CMOS circuits using sequential laterally solidified silicon thin-film transistors on plastic

Solid-state and nanoelectronic devices active and passive components in cmos-compatible technologies

Tunable on-chip inductors up to 5 GHz using patterned permalloy laminations

Compact on-chip monopole antennas on 20-/spl Omega/-cm silicon substrates for operation in the 5.8-GHz ISM band

A novel CMOS compatible L-shaped impact-ionization MOS (LI-MOS) transistor

70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)

From DRAM to SRAM with a novel sige-based negative differential resistance (NDR) device

Low-cost self-aligned SiGeC HBT module for high-performance bulk and SOI RFCMOS platforms

Modeling and simulation simulation of doping and stress effects in advanced CMOS

Understanding, modeling and optimizing vacancy engineering for stable highly boron-doped ultrashallow junctions

Ultra-thin-body fully depleted SOI metal source/drain n-MOSFETs and ITRS low-standby-power targets through 2018

Moderately doped channel multiple-finFET for logic applications

Practical finFET design considering GIDL for LSTP (low standby power) devices

Thermal phenomena in deeply scaled MOSFETs

Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology

A full self-consistent methodology for strain-induced effects characterization in silicon devices

Quantum, power, and compound semiconductor devices silicon challenges conventional iii-v light emitters

Light emitting silicon nanostructures

2 /spl mu/m emission from Si/Ge heterojunction LED and up to 1.55 /spl mu/m detection by GOI detectors with strain-enhanced features

Dislocation engineering for a silicon-based light emitter at 1.5 /spl mu/

Failure mechanisms of gallium nitride LEDs related with passivation

A novel silicon-nitride based light-emitting transistor (SiNLET): optical/electrical properties of a SONOS-type three-terminal electroluminescence device for optical communication in ULSI

Modeling and simulation system level device modeling

Analysis and implications of ic cooling for deep nanometer scale cmos technologies

Chip-level performance maximization using ASIS (application-specific interconnect structure) wiring design concept for 45 nm CMOS devices

New constraint for Vth optimization for sub 32nm node CMOS gates scaling

SOI 90-nm ring oscillator sub-ps model-hardware correlation and parasitic-aware optimization leading to 1.94-ps switching delay

The origin of variable retention time in DRAM

Program and SILC constraints on NC memories scaling: a monte carlo approach

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International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224)

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Positive bias and temperature stress induced two-stage drain current degradation in HfSiON nMOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Chan, C.T. Tang, C.J. Tahui Wang Wang, H.C.-H. Tang, D.D.
Copyright Year	2005
Description	Author affiliation: Dept. of Electron. Eng., National Chiao Tung Univ. (Chan, C.T.; Tang, C.J.; Tahui Wang)
Abstract	Positive bias and temperature (PBTI) stress induced drain current degradation in HfSiON gate dielectric nMOSFETs is investigated by using a transient measurement technique. The degradation exhibits two stages, featuring different degradation rate and stress temperature dependence. The drain current degradation in the first stage is attributed to the charging of pre-existing high-k dielectric traps while the degradation in the second stage is mainly due to additional high-k trap creation. Process effect on high-k trap growth is evaluated
Starting Page	563
Ending Page	566
File Size	321464
Page Count	4
File Format	PDF
ISBN	078039268X
DOI	10.1109/IEDM.2005.1609408
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-12-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation MOSFETs High-K gate dielectrics High K dielectric materials Temperature dependence Current measurement Stress measurement Measurement techniques Time measurement Acceleration
Content Type	Text
Resource Type	Article

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