NDLI: Monte Carlo simulation of ion implantation into topographically complex structures

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Executing system on a chip: requirements for a successful SOC implementation

Intercontinental migration of dominant technologies

Trends in semiconductor equipment, materials, and processing technology

Amorphous silicon TFT X-ray image sensors

Monolithic integration of light emitting diodes, detectors and optical fibers on a silicon wafer: a CMOS compatible optical sensor

A novel p-i-n photodetector fabricated on SIMOX for 1 GHz 2 V CMOS OEICs

640/spl times/480 back-illuminated CCD imager with improved blooming control for night vision

A 2/3" 2-M pixel progressive scan FT-CCD for digital still camera applications

Dynamic range improvement by narrow-channel effect suppression and smear reduction technologies in small pixel IT-CCD image sensors

A snap-shot CMOS active pixel imager for low-noise, high-speed imaging

Wide bandgap semiconductor power electronics

Direct measurement of gate depletion in high breakdown (405 V) AlGaN/GaN heterostructure field effect transistors

Novel high power AlGaAs/GaAs HFET with a field-modulating plate operated at 35 V drain voltage

Low-distortion GaAs-based field effect transistors with InGaP channel layer for high-voltage operation

Depletion-mode GaAs MOSFETs with negligible drain current drift and hysteresis

Improvement of off-state breakdown voltage in power GaAs MESFETs based on an accurate simulation scheme

Quasi-3D device simulation for microwave noise characterization of MOS devices

Physics-based RF noise modeling of submicron MOSFETs

BSIM3 based RTS and 1/f noise models suitable for circuit simulators

A physically based model for low-frequency noise of poly-silicon resistors

Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

ESD circuit synthesis and analysis using TCAD and SPICE

A compact SOI-MOSFET model for high temperature circuit simulation with emphasis on process and layout data

Status of single-electron memories

Room temperature single electron effects in Si quantum dot memory with oxide-nitride tunneling dielectrics

MOS memory using germanium nanocrystals formed by thermal oxidation of Si/sub 1-x/Ge/sub x/

Influence of quantum confinement effects on single electron and single hole transistors

Fabrication method for IC-oriented Si twin island single electron transistors

A multi-gate single-electron transistor and its application to an exclusive-OR gate

Shallow trench isolation for advanced ULSI CMOS technologies

Novel corner rounding process for shallow trench isolation utilizing MSTS (Micro-Structure Transformation of Silicon)

Stress analysis of shallow trench isolation for 256 M DRAM and beyond

Modeling of cumulative thermo-mechanical stress (CTMS) produced by the shallow trench isolation process for 1 Gb DRAM and beyond

Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time

Leakage current observation on irregular local PN junctions forming the tail distribution of DRAM retention characteristics, with new test structure

Local-field-enhancement model of DRAM retention failure

Ultra-thin gate oxides-performance and reliability

Reliability projection for ultra-thin oxides at low voltage

Comparison of E and 1/E TDDB models for SiO/sub 2/ under long-term/low-field test conditions

Influence of 1 nm-thick structural "strained-layer" near SiO/sub 2//Si interface on sub-4 nm-thick gate oxide reliability

Explanation of stress-induced damage in thin oxides

A detailed study of soft- and pre-soft-breakdowns in small geometry MOS structures

Structural dependence of dielectric breakdown in ultra-thin gate oxides and its relationship to soft breakdown modes and device failure

Point contact conduction at the oxide breakdown of MOS devices

A high performance 180 nm generation logic technology

A novel 6T-SRAM cell technology designed with rectangular patterns scalable beyond 0.18 /spl mu/m generation and desirable for ultra high speed operation

A novel 0.20 /spl mu/m full CMOS SRAM cell using stacked cross couple with enhanced soft error immunity

A 0.2-/spl mu/m bipolar-CMOS technology on bonded SOI with copper metallization for ultra high-speed processors

An RF BiCMOS process using high f/sub SR/ spiral inductor with premetal deep trenches and a dual recessed bipolar collector sink

1.8 million transistor CMOS ASIC fabricated in a SiGe BiCMOS technology

30-nm-gate InAlAs/InGaAs HEMTs lattice-matched to InP substrates

Improvement of DC, low frequency and reliability properties of InAlAs/InGaAs InP-based HEMTs by means of an InP etch stop layer

Hydrogen degradation in InP HEMTs

Metamorphic In/sub x/Al/sub 1-x/As/In/sub x/Ga/sub 1-x/As HEMTs on GaAs substrate: the influence of In composition

Deep submicron PHEMTs characterization with spectrally resolved carrier recombination imaging

A new dynamic model for the kink effect in InAlAs/InGaAs HEMTs

Integrated a-Si:H/pentacene inorganic/organic complementary circuits

Tri-layer a-Si:H integrated circuits on polymeric substrates

Polysilicon thin film transistors fabricated at 100/spl deg/C on a flexible plastic substrate

Hydrogen plasma-enhanced crystallization of amorphous silicon for low-temperature polycrystalline silicon TFT's

Improved stability of polysilicon thin-film transistors under self-heating and high endurance EEPROM cells for systems-on-panel

Highly reliable liquid-phase deposited SiO/sub 2/ with nitrous oxide plasma post-treatment for low temperature processed poly-Si TFTs

A conductivity modulated high voltage polycrystalline silicon thin film transistor with improved on state and transient performance

Modeling of grain size variation effects in polycrystalline thin film transistors

Within-chip variability analysis

Real time on-chip characterization of time delay arising from multi-level-metallization: decoupling of pure charging and drift-and-charging

Impact of crosstalk on delay time and a hierarchy of interconnects

Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections

A fast 3D modeling approach to parasitics extraction of bonding wires for RF circuits

Equipotential shells for efficient partial inductance extraction

Process- and geometry-scalable bipolar transistor and transmission line models for Si and SiGe MMICs in the 5-22 GHz range

Deposition and simulation of refractory barriers into high aspect ratio re-entrant features using directional sputtering

Achieving high microprocessor manufacturing output-the Copy Exactly! method

Foundry technology for the next decade

Cost-effective cleaning for advanced Si-processing

Physical and chemical analytical instruments far failure analyses in Gbit devices

0.1 /spl mu/m level contact hole pattern formation with KrF lithography by resolution enhancement lithography assisted by chemical shrink (RELACS)

Dry etch sequencing induced gate oxide degradation due to metallic contamination in 0.25 /spl mu/m CMOS manufacturing

Threshold pressure and its influence in chemical mechanical polishing for IC fabrication

Multiple-thickness gate oxide and dual-gate technologies for high-performance logic-embedded DRAMs

A new DRAM cell technology using merged process with storage node and memory cell contact for 4 Gb DRAM and beyond

Future directions for DRAM memory cell technology

FRAM cell design with high immunity to fatigue and imprint for 0.5 /spl mu/m 3 V 1T1C 1M bit FRAM

Capacitor-on-metal/via-stacked-plug (CMVP) memory cell for 0.25 /spl mu/m CMOS embedded FeRAM

Impact of neutron flux on soft errors in MOS memories

Ultra thin (<20 /spl Aring/) CVD Si/sub 3/N/sub 4/ gate dielectric for deep-sub-micron CMOS devices

High quality ultra-thin TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectric for giga scale MOS technology

SiON/Ta/sub 2/O/sub 5//TiN gate-stack transistor with 1.8 nm equivalent SiO/sub 2/ thickness

In-situ barrier formation for high reliable W/barrier/poly-Si gate using denudation of WN/sub x/ on polycrystalline Si

Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond

An ultra-low resistance and thermally stable W/pn-poly-Si gate CMOS technology using Si/TiN buffer layer

Improving gate oxide integrity (GOI) of a W/WNx/dual-poly Si stacked-gate by using wet-hydrogen oxidation in 0.14-/spl mu/m CMOS devices

Scalability of SOI technology into 0.13 /spl mu/m 1.2 V CMOS generation

Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation

Pseudo-SOI: P-N-P-channel-doped bulk MOSFET for low-voltage high-performance applications

Novel low capacitance sidewall elevated drain dynamic threshold voltage MOSFET (LCSED) for ultra low power dual gate CMOS technology

A new dynamic-threshold SOI device having an embedded resistor and a merged body-bias-control transistor

High performance electrically induced body dynamic threshold SOI MOSFET (EIB-DTMOS) with large body effect and low threshold voltage

Transistors and tunnel diodes for analog/mixed-signal circuits and embedded memory

Arrays of resonant tunnelling diodes defined by in-situ focused ion beam lithography: potential millimetre wave/microwave power sources?

Tetrahedral shaped recess channel HEMT with a floating quantum dot gate

Room temperature operating infrared (8-12 /spl mu/m) photodetector with InAs quantum dots in modulation doped heterostructures

Spectral hole burning of InAs self-assembled quantum dots written by two different lasers

Room temperature Coulomb oscillation and memory effect for single electron memory made by pulse-mode AFM nano-oxidation process

A resonant terahertz detector utilizing a high electron mobility transistor

Monolithic arrays of micromachined pixels for infrared applications

A high fill-factor IR bolometer using multi-level electrothermal structures

High-selectivity single-chip spectrometer for operation at visible wavelengths

Micromechanical mixer and filters

Trench oxide isolated single crystal silicon micromachined accelerometer

In-plane sensitive vertical trench-Hall device

Novel thermal microactuator based on CVD-diamond films

Defect and dopant diffusion in ion implanted silicon: an atomic scale simulation approach

Predictive simulation of transient activation processes in boron-doped silicon structures

Experiments and modeling of boron segregation to {311} defects and initial rapid enhanced boron diffusion induced by self-implantation in Si

Beyond TED: understanding boron shallow junction formation

Modeling solid source boron diffusion for advanced transistor applications

A calibrated model for trapping of implanted dopants at material interface during thermal annealing

Monte Carlo simulation of ion implantation into topographically complex structures

New analytic models and efficient parameter extraction for computationally efficient 1-D and 2-D ion implantation modeling

Progress in RF inductors on silicon-understanding substrate losses

Application of a new circuit design oriented Q extraction technique to inductors in silicon ICs

Modeling and characterization of on-chip transformers

A novel buried oxide isolation for monolithic RF inductors on silicon

On-chip spiral inductors with diffused shields using channel-stop implant

High-performance electroplated solenoid-type integrated inductor (SI/sup 2/) for RF applications using simple 3D surface micromachining technology

Novel high-Q bondwire inductor for MMIC

Two-dimensional dopant profiling of a 60 nm gate length nMOSFET using scanning capacitance microscopy

Direct measurement of l/sub eff/ and channel profile in MOSFETs using 2-D carrier profiling techniques

A new evaluation method of plasma process-induced Si substrate damage by the voltage shift under constant current injection at metal/Si interface

Direct detecting of dynamic floating-body effects in SOI circuits by backside electron beam testing

Remote charge scattering in MOSFETs with ultra-thin gate dielectrics

Importance of Si-N atomic configuration at the Si/oxynitride interfaces on the performance of scaled MOSFETs

Experimental signature and physical mechanisms of substrate enhanced gate current in MOS devices

Sub-5 nm multiple-thickness gate oxide technology using oxygen implantation

Multiple gate oxide thickness for 2 GHz system-on-a-chip technologies

Radical oxygen (O/sup */) process for highly-reliable SiO/sub 2/ with higher film-density and smoother SiO/sub 2//Si interface

Impact of nitridation engineering on microscopic SILC characteristics of sub-10-nm tunnel dielectrics

Antenna device reliability for ULSI processing

Gate quality doped high K films for CMOS beyond 100 nm: 3-10 nm Al/sub 2/O/sub 3/ with low leakage and low interface states

Ultra thin high quality Ta/sub 2/O/sub 5/ gate dielectric prepared by in-situ rapid thermal processing

Progress toward 10 nm CMOS devices

Accurate characterization of electron and hole inversion-layer capacitance and its impact on low voltage operation of scaled MOSFETs

A 1.2 V, 0.1 /spl mu/m gate length CMOS technology: design and process issues

High-performance sub-0.08 /spl mu/m CMOS with dual gate oxide and 9.7 ps inverter delay

A study of ultra shallow junction and tilted channel implantation for high performance 0.1 /spl mu/m pMOSFETs

Channel profile engineering of 0.1 /spl mu/m-Si MOSFETs by through-the-gate implantation

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A 1.9-/spl mu/m/sup 2/ loadless CMOS four-transistor SRAM cell in a 0.18-/spl mu/m logic technology

Advanced performance of small-scaled InGaP/GaAs HBT's with f/sub T/ over 150 GHz and f/sub max/ over 250 GHz

Transferred-substrate HBTs with 250 GHz current-gain cutoff frequency

High-gain GaInP/GaAs HBT monolithic transimpedance amplifier for high-speed optoelectronic receivers

Broadly-tunable narrow-linewidth micromachined laser/photodetector and phototransistor

Failure analysis of travelling wave MSM distributed photodetectors

Investigation of the space charge effect in the quantum well infrared photodetector

Lateral thinking about power devices (LDMOS)

A new generation of high voltage MOSFETs breaks the limit line of silicon

A lateral insulated gate bipolar transistor employing the self-align sidewall implanted n/sup +/ source

Backside laserprober characterization of thermal effects during high current stress in smart power ESD protection devices

Breakdown and low-temperature anomalous effects in 6H SiC JFETs

SiGe fast-switching power diodes

Si/SiGe:C heterojunction bipolar transistors in an epi-free well, single-polysilicon technology

Transconductance enhancement in deep submicron strained Si n-MOSFETs

Two-dimensional dopant profiling of deep submicron MOS devices by electron holography

Validation of two-dimensional implant and diffusion profiles using novel scanning capacitance microscope sample preparation and deconvolution techniques

Characterization of arsenic dose loss at the Si/SiO/sub 2/ interface using high resolution X-ray photoelectron spectrometry

Suppression of reverse short channel effect by a buried carbon layer

An integrated approach for accurate simulation and modeling of the silicide-source/drain structure and the silicide-diffusion contact resistance

Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model

Straddle-gate transistor: changing MOSFET channel length between off- and on-state towards achieving tunneling-defined limit of field-effect

Optimization guidelines for epitaxial collectors of advanced BJT's with improved breakdown voltage and speed

Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs

A versatile 0.25 micron CMOS technology

1.5 nm equivalent thickness Ta/sub 2/O/sub 5/ high-k dielectric with rugged Si suited for mass production of high density DRAMs

High levels of IC manufacturability: one of the necessary prerequisites of the 1997 SIA Roadmap vision

Statistical modeling and circuit simulation for design for manufacturing

Modeling the effects of manufacturing variation on high-speed microprocessor interconnect performance

Explanation and quantitative model for the matching behaviour of poly-silicon resistors

CMOS metal replacement gate transistors using tantalum pentoxide gate insulator

PVD TiN metal gate MOSFETs on bulk silicon and fully depleted silicon-on-insulator (FDSOI) substrates for deep sub-quarter micron CMOS technology

High performance metal gate MOSFETs fabricated by CMP for 0.1 /spl mu/m regime

25 nm CMOS design considerations

Reduced gate leakage current and boron penetration of 0.18 /spl mu/m 1.5 V MOSFETs using integrated RTCVD oxynitride gate dielectric

Effect of barrier layer on the electrical and reliability characteristics of high-k gate dielectric films

(Ba,Sr)TiO/sub 3/ capacitor technology for Gbit-scale DRAMs

All perovskite capacitor (APEC) technology for (Ba,Sr)TiO/sub 3/ capacitor scaling toward 0.10 /spl mu/m stacked DRAMs

A manufacturable integration technology of sputter-BST capacitor with a newly proposed thick Pt electrode

Integration processes of (Ba,Sr)TiO/sub 3/ capacitor for 1 Gb and beyond [DRAMs]

Sputtering process design of PZT capacitors for stable FeRAM operation

Advanced dielectrics for gate oxide, DRAM and RF capacitors

The best combination of aluminum and copper interconnects for a high performance 0.18 /spl mu/m CMOS logic device

Interconnect design strategy: structures, repeaters and materials toward 0.1 /spl mu/m ULSIs with a giga-hertz clock operation

Advanced interconnect scheme analysis: real impact of technological improvements

RC delay reduction of 0.18 /spl mu/m CMOS technology using low dielectric constant fluorinated amorphous carbon

Novel co-sputtered fluorinated amorphous carbon films for sub-0.25 /spl mu/m low /spl kappa/ damascene multilevel interconnect applications

Shared tungsten structures for FEOL/BEOL compatibility in logic-friendly merged DRAM

100 nm aperture field emitter arrays for low voltage applications

Si field emitter array with 90-nm-diameter gate holes

An efficient 3-dimensional CAD tool for field-emission devices

Analysis of low threshold field-emission from conjugated polymers for displays

Polysilicon VGA active matrix OLED displays-technology and performance

The impact of the transient response of organic light emitting diodes on the design of active matrix OLED displays

Thermal, self-heating and kink effects in a-Si:H thin film transistors

Energy dependent electron and hole impact ionization in Si bipolar transistors

The origin of secondary electron gate current: a multiple-stage Monte Carlo study for scaled, low-power flash memory

Monte Carlo simulation of hot-carrier degradation in scaled MOS transistors for VLSI technology

Full-band Monte Carlo simulation of a 0.12 /spl mu/m-Si-PMOSFET with and without a strained SiGe-channel

A new model of tunnelling current and SILC in ultra-thin oxides

Monte Carlo simulation of stress-induced leakage current by hopping conduction via multi-traps in oxide

Analysis of the gate voltage fluctuations in ultra-thin gate oxides after soft breakdown

Transistor matching in analog CMOS applications

Threshold voltage fluctuation induced by direct tunnel leakage current through 1.2-2.8 nm thick gate oxides for scaled MOSFETs

A study of flicker noise in n- and p-MOSFETs with ultra-thin gate oxide in the direct-tunneling regime

0.12 /spl mu/m raised gate/source/drain epitaxial channel NMOS technology

Hot carrier reliability considerations in the integration of dual gate oxide transistor process on a sub-0.25 /spl mu/m CMOS technology for embedded applications

Multi-level metal CMOS manufacturing with deuterium for improved hot carrier reliability

Reliability of vertical MOSFETs for gigascale memory applications

A novel high-frequency quasi-SOI power MOSFET for multi-gigahertz applications

Device design methodology to optimize low-frequency noise in advanced SOI CMOS technology for RF ICs

A 31 GHz f/sub max/ lateral BJT on SOI using self-aligned external base formation technology

Record power added efficiency of bipolar power transistors for low voltage wireless applications

An effective gate resistance model for CMOS RF and noise modeling

Process induced damage on RFCMOS

Flash memories: where we were and where we are going

Novel 0.44 /spl mu/m/sup 2/ Ti-salicide STI cell technology for high-density NOR flash memories and high performance embedded application

A novel 4.6F/sup 2/ NOR cell technology with lightly doped source (LDS) junction for high density flash memories

An advanced flash memory technology on SOI

Low voltage, low current, high speed program step split gate cell with ballistic direct injection for EEPROM/flash

Flexible hot-electron programming of flash memories

0.13 /spl mu/m MONOS single transistor memory cell with separated source lines

SOI MOSFET on low cost SPIMOX substrate

High thermal stability and low junction leakage current of Ti capped Co salicide and its feasibility for high thermal budget CMOS devices

Ultra-shallow junction formation by outdiffusion from implanted oxide

A high performance 1.5 V, 0.10 /spl mu/m gate length CMOS technology with scaled copper metallization

Integration of trench DRAM into a high-performance 0.18 /spl mu/m logic technology with copper BEOL

A novel high-gain CMOS image sensor using floating N-well/gate tied PMOSFET

31% absolute external quantum efficiency 850-nm LEDs and their modulation behavior

Embedded DRAM technology compatible to the 0.13 /spl mu/m high-speed logics by using Ru pillars in cell capacitors and peripheral vias

A folded-channel MOSFET for deep-sub-tenth micron era

Si-based interband tunneling devices for high-speed logic and low power memory applications

A 1.1 nm oxide equivalent gate insulator formed using TiO/sub 2/ on nitrided silicon

Ultra-thin gate oxides and ultra-shallow junctions for high performance, sub-100 nm pMOSFETs

PMD (preferential metal deposition) aluminum process for 16 giga-bit DRAM and beyond

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