NDLI: Evaluation of 1's complement arithmetic for the implementation low power CMOS floating point adders

Content Provider	IEEE Xplore Digital Library
Author	Pillai, R.V.K. Al-Khalili, D. Al-Khalili, A.J.
Copyright Year	1997
Description	Author affiliation: Concordia Univ., Montreal, Que., Canada (Pillai, R.V.K.)
Abstract	In CMOS logic implementations, the architecture of functional units reflects the algorithmic cause effect relations as far as logic functionality, structural complexity, power consumption and speed of operation are concerned. The paper addresses the architectural evaluation of arithmetic units based on 1's complement algorithms for the implementation of low power floating point units. Our investigations suggest the suitability of 1's complement adders for the realization of low power floating point adders/subtracters, accumulators and multiply accumulators. The power consumption and silicon area of 1's complement adders that realize functions of the type \|A-B\| involving integer data A and B, are around 50% of that of their 2's complement counterparts.
Starting Page	153
Ending Page	156
File Size	486457
Page Count	4
File Format	PDF
ISBN	0780337166
ISSN	08407789
DOI	10.1109/CCECE.1997.614813
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-05-25
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Floating-point arithmetic CMOS logic circuits Energy consumption Silicon Algorithm design and analysis Educational institutions Bismuth Logic design Power demand Data conversion
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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