NDLI: Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers

Content Provider	IEEE Xplore Digital Library
Author	Morales-Sandoval, M. Diaz-Perez, A.
Copyright Year	2013
Description	Author affiliation: Res. Center for Adv. Studies, Nat. Polytech. Inst., Ciudad Victoria, Mexico (Morales-Sandoval, M.; Diaz-Perez, A.)
Abstract	This work describes FPGA hardware architectures of $GF(2^{m})$ multipliers being more compact than a bit-serial multiplier and outperforming software counterparts. The proposed multiplier is more compact than a hardware implementation of the bit-serial approach, considered the most compact one. Also, the designs proposed still outperform software counterparts. For field multiplication, the multiplicand and modulus are parsed in digits of size d while the multiplier is parsed in digits of size D. Thus, the area complexity of the multiplier is mainly determined by the digits {D, d}, not by the order of the finite field m, which affects only the latency and thus the throughput. This approach allows to implement $GF(2^{m})$ multipliers for any finite field with practically the same amount of FPGA resources. Several multiplier versions were implemented using different combinations for {D, d} in order to find the most compact designs while achieving better performance and efficiency than a bit-serial multiplier. From a hardware implementation in the xc3s1500 FPGA for the finite field $GF(2^{233}),$ the most efficient multiplier is obtained using the digits {D=6, d= 12}, requiring 70% less area resources than a bit-serial multiplier.
Starting Page	649
Ending Page	652
File Size	246692
Page Count	4
File Format	PDF
ISBN	9781479929788
DOI	10.1109/DSD.2013.124
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Polynomials Throughput Hardware Computer architecture Software Compact GF(2m) multiplication FPGA Finite Field
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m)

Area/performance evaluation of digit-digit $GF(2^{K})$ multipliers on FPGAS

A hardware pipelined architecture of a scalable Montgomery modular multiplier over $GF(2^{m})$

Hardware Implementation of Fast Division Algorithm for $GF(2^{m})$

A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

High-speed architectures for GHASH based on efficient bit-parallel multipliers

High-throughput hardware-efficient digit-serial architecture for field multiplication over $GF(2^{m})$

High Throughput, Pipelined Implementation of AES on FPGA

Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers

Similar Documents

Small FPGA Based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m)

Area/performance evaluation of digit-digit $GF(2^{K})$ multipliers on FPGAS

A hardware pipelined architecture of a scalable Montgomery modular multiplier over $GF(2^{m})$

Hardware Implementation of Fast Division Algorithm for $GF(2^{m})$

A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation

High-Throughput Finite Field Multipliers Using Redundant Basis for FPGA and ASIC Implementations

High-speed architectures for GHASH based on efficient bit-parallel multipliers

High-throughput hardware-efficient digit-serial architecture for field multiplication over $GF(2^{m})$

High Throughput, Pipelined Implementation of AES on FPGA

Compact FPGA-Based Hardware Architectures for GF(2^m) Multipliers