NDLI: At-speed testing of SOC ICs

Content Provider	IEEE Xplore Digital Library
Author	Vorisek, V. Koch, T. Fischer, H.
Copyright Year	2004
Description	Author affiliation: Semicond. Products Sector, Multimedia Design Center, Munich, Germany (Vorisek, V.; Koch, T.; Fischer, H.)
Abstract	This paper discusses the aspects and associated requirements of design and implementation of at-speed scan testing. It also demonstrates some important vector generation and implementation procedures based on a real design. An innovative method of scan pattern timing creation based on the results from static timing analysis is presented. The paper also describes the usage of a clock control module on J750 tester, which creates fast clock by combining two tester channels with high edge placement accuracy. These methods allow a short test pattern preparation time and the use of low-cost test equipment, while providing the high quality at-speed testing.
Sponsorship	EDAA, EDA Consortium, IEEE Comput. Soc. TTTC IEEE Comput. Soc. DATC ECSI ACM/SIGDA RAS
Starting Page	120
Ending Page	125
File Size	268338
Page Count	6
File Format	PDF
ISBN	0769520855
ISSN	15301591
DOI	10.1109/DATE.2004.1269217
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-02-16
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit faults Timing Automatic test pattern generation Automatic testing Circuit testing Clocks Frequency Delay effects Costs Manufacturing automation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Advanced automatic test pattern generation techniques for path delay faults

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Low-capture-power test generation for scan-based at-speed testing

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

Timing-based delay test for screening small delay defects

Delay testing based on transition faults propagated to all reachable outputs

High-frequency, at-speed scan testing

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

At-speed transition fault testing with low speed scan enable

At-speed testing of SOC ICs

Similar Documents

Advanced automatic test pattern generation techniques for path delay faults

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing

Low-capture-power test generation for scan-based at-speed testing

Power-Aware At-Speed Scan Test Methodology for Circuits with Synchronous Clocks

Timing-based delay test for screening small delay defects

Delay testing based on transition faults propagated to all reachable outputs

High-frequency, at-speed scan testing

Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects

At-speed transition fault testing with low speed scan enable

At-speed testing of SOC ICs