NDLI: Crosstalk noise in future digital CMOS circuits

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Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078)

Proceedings Design, Automation and Test in Europe

Crosstalk noise in future digital CMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Werner, C. Gottsche, R. Worner, A. Ramacher, U.
Copyright Year	2001
Description	Author affiliation: Corp. Res, Infineon Technol., Munich, Germany (Werner, C.)
Abstract	This paper presents simulation results for crosstalk noise in future CMOS generations down to 35 nm features. The noise voltage is calculated from circuit simulations with lumped RLC networks and static CMOS cells. A static noise margin is derived from inverter characteristics of NAND and NOR gates and a critical wirelength is calculated from considering statistical variations in the chip manufacturing process. The model agrees well with measurements on a quarter micron testchip and predicts a drastic drop of critical wirelengths to 50-60 /spl mu/m after the 100 nm technology generation.
Sponsorship	EDAA
Starting Page	331
Ending Page	335
File Size	283658
Page Count	5
File Format	PDF
ISBN	0769509932
ISSN	15301591
DOI	10.1109/DATE.2001.915045
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-03-13
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Crosstalk CMOS digital integrated circuits Circuit simulation Circuit noise RLC circuits Voltage Inverters Manufacturing processes Semiconductor device modeling Predictive models
Content Type	Text
Resource Type	Article

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