NDLI: Coordinated transformations for high-level synthesis of high performance microprocessor blocks

Content Provider	IEEE Xplore Digital Library
Author	Gupta, S. Kam, T. Kishinevsky, M. Rotem, S. Savoiu, N. Dutt, N. Gupta, R. Nicolau, A.
Copyright Year	2002
Description	Author affiliation: Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA (Gupta, S.; Kam, T.; Kishinevsky, M.; Rotem, S.)
Abstract	High performance microprocessor designs are partially characterized by functional blocks consisting of a large number of operations that are packed into very few cycles (often single-cycle) with little or no resource constraints but tight bounds on the cycle time. Extreme parallelization, conditional and speculative execution of operations is essential to meet the processor performance goals. However, this is a tedious task for which classical high-level synthesis (HLS) formulations are inadequate and thus rarely used. In this paper, we present a new methodology for application of HLS targeted to such microprocessor functional blocks that can potentially speed up the design space exploration for microprocessor designs. Our methodology consists of a coordinated set of source-level and fine-grain parallelizing compiler transformations that targets these behavioral descriptions, specifically loop constructs in them and enables efficient chaining of operations and high-level synthesis of the functional blocks. As a case study in understanding the complexity and challenges in the use of HLS, we walk the reader through the detailed design of an instruction length decoder drawn from the Pentium/spl reg/-family of processors. The chief contribution of this paper is formulation of a domain-specific methodology for application of high-level synthesis techniques to a domain that rarely, if ever, finds use for it.
Sponsorship	ACM EDA Consortium IEEE SSCS
Starting Page	898
Ending Page	903
File Size	944007
Page Count	6
File Format	PDF
ISBN	1581134614
ISSN	0738100X
DOI	10.1109/DAC.2002.1012749
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-06-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	High level synthesis Microprocessors Delay Processor scheduling Pipeline processing Permission Embedded computing High performance computing Design automation Space exploration
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Coordinated transformations for high-level synthesis of high performance microprocessor blocks

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