NDLI: Fault characterizations and design-for-testability technique for detecting I/sub DDQ/ faults in CMOS/BiCMOS circuits

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Fault characterizations and design-for-testability technique for detecting I/sub DDQ/ faults in CMOS/BiCMOS circuits

Content Provider	IEEE Xplore Digital Library
Author	Raahemifar, K. Ahmadi, M.
Copyright Year	2001
Description	Author affiliation: Electr. & Comput. Eng. Dept., Ryerson Polytech. Inst., Toronto, Ont., Canada (Raahemifar, K.)
Abstract	This paper provides the results of a simulation-based fault characterization study of CMOS/BiCMOS logic families. We show that most of the shorts cause l/sub DDQ/ faults, while open defects result in delay or stuck-open faults. We propose a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated.
Starting Page	313
Ending Page	316
File Size	445217
Page Count	4
File Format	PDF
ISBN	1581132972
ISSN	0738100X
DOI	10.1109/DAC.2001.156157
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Fault detection Circuit faults BiCMOS integrated circuits CMOS logic circuits Electrical fault detection Circuit simulation Circuit testing Delay Semiconductor device modeling Permission
Content Type	Text
Resource Type	Article

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