NDLI: Lower bounds on test resources for scheduled data flow graphs

Please wait, while we are loading the content...

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC)

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC)

2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

DAC Design Automation Conference 2012

2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC)

Design Automation Conference

2009 46th ACM/IEEE Design Automation Conference

2008 45th ACM/IEEE Design Automation Conference

2007 44th ACM/IEEE Design Automation Conference

2006 43rd ACM/IEEE Design Automation Conference

Proceedings. 42nd Design Automation Conference, 2005.

Proceedings. 41st Design Automation Conference, 2004.

Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451)

Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324)

Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232)

Proceedings 37th Design Automation Conference

Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361)

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

Proceedings of the 34th Design Automation Conference

33rd Design Automation Conference Proceedings, 1996

Proceedings of 33rd Design Automation Conference

Package and interconnect modeling of the HFA3624, a 2.4 GHz RF to IF converter

HEAT: hierarchical energy analysis tool

Opportunities and obstacles in low-power system-level CAD

POSE: power optimization and synthesis environment

Early power exploration-a World Wide Web application [high-level design]

Behavioral synthesis

A register file and scheduling model for application specific processor synthesis

Optimized code generation of multiplication-free linear transforms

Concurrent analysis techniques for data path timing optimization

HDL optimization using timed decision tables

Efficient partial enumeration for timing analysis of asynchronous systems

Verification of asynchronous circuits using time Petri net unfolding

Methodology and tools for state encoding in asynchronous circuit synthesis

A technique for synthesizing distributed burst-mode circuits

Espresso-HF: a heuristic hazard-free minimizer for two-level logic

Synthesis of hazard-free customized CMOS complex-gate networks under multiple-input changes

Partitioning of VLSI circuits and systems

New spectral linear placement and clustering approach

Characterization and parameterized random generation of digital circuits

A probability-based approach to VLSI circuit partitioning

Verification of electronic systems

Design considerations and tools for low-voltage digital system design

VAMP: a VHDL based concept for accurate modeling and post layout timing simulation of electronic systems

A systematic technique for verifying critical path delays in a 300 MHz Alpha CPU design using circuit simulation

High-level synthesis for testability: a survey and perspective

Introspection: a low overhead binding technique during self-diagnosing microarchitecture synthesis

Lower bounds on test resources for scheduled data flow graphs

Symphony: a simulation backplane for parallel mixed-mode co-simulation of VLSI systems

Oscillation control in logic simulation using dynamic dominance graphs

Compact vector generation for accurate power simulation

Improving the efficiency of power simulators by input vector compaction

Efficient communication in a design environment

A description language for design process management

Improved tool and data selection in task management

Application of a Markov model to the measurement, simulation, and diagnosis of an iterative design process

The SPICE FET models: pitfalls and prospects (Are you an educated model consumer?)

Tutorial: design of a logic synthesis system

On solving covering problems [logic synthesis]

A new complete diagnosis patterns for wiring interconnects

A satisfiability-based test generator for path delay faults in combinational circuits

On static compaction of test sequences for synchronous sequential circuits

An O(n) algorithm for transistor stacking with performance constraints

Use of sensitivities and generalized substrate models in mixed-signal IC design

RTL Emulatlon: The Next Leap In System Verification

Equation-based behavioral model generation for nonlinear analog circuits

Multilevel logic synthesis for arithmetic functions

Synthesis by spectral translation using Boolean decision diagrams

Delay minimal decomposition of multiplexers in technology mapping

Error correction based on verification techniques

Layout driven selecting and chaining of partial scan flip-flops

Test point insertion: scan paths through combinational logic

Area efficient pipelined pseudo-exhaustive testing with retiming

Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations

Homotopy techniques for obtaining a DC solution of large-scale MOS circuits

Efficient AC and noise analysis of two-tone RF circuits

Synthesis tools for Mixed-Signal ICs: progress on frontend and backend strategies

Code generation and analysis for the functional verification of microprocessors

Innovative verification strategy reduces design cycle time for high-end SPARC processor

Hardware emulation for functional verification of K5

Functional verification methodology for the PowerPC 604 microprocessor

I'm done simulating; now what? Verification coverage analysis and correctness checking of the DECchip 21164 Alpha microprocessor

Glitch analysis and reduction in register transfer level power optimization

An effective power management scheme for RTL design based on multiple clocks

Power optimization in programmable processors and ASIC implementations of linear systems: transformation-based approach

Scheduling techniques to enable power management

Electromigration reliability enhancement via bus activity distribution

A sparse image method for BEM capacitance extraction

A parallel precorrected FFT based capacitance extraction program for signal integrity analysis

Multipole accelerated capacitance calculation for structures with multiple dielectrics with high permittivity ratios

Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance

Efficient full-wave electromagnetic analysis via model-order reduction of fast integral transforms

Useful-skew clock routing with gate sizing for low power design

Sizing of clock distribution networks for high performance CPU chips

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

Constructing lower and upper bounded delay routing trees using linear programming

Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

How to write Awk and Perl scripts to enable your EDA tools to work together

The automatic generation of functional test vectors for Rambus designs

Functional verification methodology of Chameleon processor

Experience in designing a large-scale multiprocessor using field-programmable devices and advanced CAD tools

Power Estimation of Cell-Based CMOS Circuits

A new hybrid methodology for power estimation

A statistical approach to the estimation of delay-dependent switching activities in CMOS combinational circuits

Engineering change in a non-deterministic FSM setting

Identifying sequential redundancies without search

A fast state reduction algorithm for incompletely specified finite state machines

Symbolic optimization of FSM networks based on sequential ATPG techniques

Module compaction in FPGA-based regular datapaths

Network partitioning into tree hierarchies

Efficient approximation algorithms for floorplan area minimization

Optimal wire-sizing formula under the Elmore delay model

VLSI design and system level verification for the Mini-Disc

Design methodologies for consumer-use video signal processing LSIs

Design methodology for analog high frequency ICs

Issues and answers in CAD tool interoperability

The design of mixed hardware/software systems

Constructing application-specific heterogeneous embedded architectures from custom HW/SW applications

A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts

Analysis of RC interconnections under ramp input

An AWE technique for fast printed circuit board delays

RC-interconnect macromodels for timing simulation

iCET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips

Techniques for verifying superscalar microprocessors

A scalable formal verification methodology for pipelined microprocessors

State reduction using reversible rules

Formal verification of embedded systems based on CFSM networks

Combined control flow dominated and data flow dominated high-level synthesis

FADIC: architectural synthesis applied in IC design

Domain-specific high-level modeling and synthesis for ATM switch design using VHDL

Using register-transfer paths in code generation for heterogeneous memory-register architectures

Address calculation for retargetable compilation and exploration of instruction-set architectures

Analysis of operation delay and execution rate constraints for embedded systems

Efficient software performance estimation methods for hardware/software codesign

An explicit RC-circuit delay approximation based on the first three moments of the impulse response

Modeling the effects of temporal proximity of input transitions on gate propagation delay and transition time

Optimal clock skew scheduling tolerant to process variations

An efficient equivalence checker for combinational circuits

High performance BDD package by exploiting memory hierarchy

Implementation of an efficient parallel BDD package

Word level model checking-avoiding the Pentium FDIV error

Formal verification of PowerPC arrays using symbolic trajectory evaluation

RuleBase: an industry-oriented formal verification tool

Bit-level analysis of an SRT divider circuit

Integrating formal verification methods with a conventional project design flow

A system design methodology for software/hardware co-development of telecommunication network applications

A strategy for real-time kernel support in application-specific HW/SW embedded architectures

Software development in a hardware simulation environment

Compiled HW/SW co-simulation

Stochastic sequential machine synthesis targeting constrained sequence generation

Energy characterization based on clustering

Architectural retiming: pipelining latency-constrained circuits

Optimizing systems for effective block-processing: the k-delay problem

Optimal clock period FPGA technology mapping for sequential circuits

Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design

A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs

New algorithms for gate sizing: a comparative study

Post-layout optimization for deep submicron design

Enhanced network flow algorithm for yield optimization

Hierarchical electromigration reliability diagnosis for VLSI interconnects

Using articulation nodes to improve the efficiency of finite-element based resistance extraction

Extracting circuit models for large RC interconnections that are accurate up to a predefined signal frequency

VHDL and Verilog compared and contrasted-plus modeled example written in VHDL, Verilog and C

VHDL development system and coding standard

An exact algorithm for low power library-specific gate re-sizing

Reducing power dissipation after technology mapping by structural transformations

Desensitization for power reduction in sequential circuits

Serial fault emulation

Partial scan design based on circuit state information

Pseudorandom-pattern test resistance in high-performance DSP datapaths

Hot-carrier reliability enhancement via input reordering and transistor sizing

A methodology for concurrent fabrication process/cell library optimization

Computing parametric yield adaptively using local linear models

Conference Author/ Panelist Index

32nd Design Automation Conference

31st Design Automation Conference

[1992] Proceedings 29th ACM/IEEE Design Automation Conference

28th ACM/IEEE Design Automation Conference

27th ACM/IEEE Design Automation Conference

26th ACM/IEEE Design Automation Conference

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

24th ACM/IEEE Design Automation Conference

23rd ACM/IEEE Design Automation Conference

22nd ACM/IEEE Design Automation Conference

21st Design Automation Conference Proceedings

20th Design Automation Conference Proceedings

19th Design Automation Conference

18th Design Automation Conference

17th Design Automation Conference

16th Design Automation Conference

15th Design Automation Conference

30th ACM/IEEE Design Automation Conference

Lower bounds on test resources for scheduled data flow graphs

Content Provider	IEEE Xplore Digital Library
Author	Parulkar, I. Gupta, S.K. Breuer, M.A.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA (Parulkar, I.)
Abstract	Lower bound estimations of resources at various stages of high-level synthesis are essential to guide synthesis algorithms towards optimal solutions. In this paper we present lower bounds on the number of test resources (i.e. test pattern generators, signature analyzers and CBILBO registers) required to test a synthesized data path using built-in self-test (BIST). The estimations are performed on scheduled data flow graphs and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of test resources to test itself.
Starting Page	143
Ending Page	148
File Size	796256
Page Count	6
File Format	PDF
ISBN	0780332946
ISSN	0738100X
DOI	10.1109/DAC.1996.545561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-06-03
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flow graphs Built-in self-test Automatic testing Logic testing Permission System testing Test pattern generators Pattern analysis Performance evaluation High level synthesis
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: ndl-support@iitkgp.ac.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in