NDLI: Delay macromodels for the timing analysis of GaAs DCFL

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Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition

Proceedings of EURO-DAC. European Design Automation Conference

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

Proceedings EURO-DAC '92: European Design Automation Conference

VHDL intermediate form standardization: process, issues and status

The design cube-a model for VHDL designflow representation

Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M

Challenges in the analysis of VHDL

Using VHDL for datapath synthesis

Synthesis of VHDL arrays on RAM cells

Subtype concept of VHDL for synthesis constraints

VHDL analog extensions: process, issues, and status

Towards a standard VHDL synthesis package

Providing a VHDL-interface for proof systems

Temporal verification of behavioral descriptions in VHDL

VHDL intermediate format standardization activity: status and trends

Multi-kernel simulation description within VHDL

Interest of a VHDL native environment

Selected aspects of component modeling

Towards a common RT-level subset of VHDL

Synchronous design in VHDL

VHDL 1076-1992 languages changes

Analysis of user requirements

1992 VHDL standardization overview

Design of complex systems with a VHDL based methodology

Test generation for I/sub DDQ/ testing and leakage fault detection in CMOS circuits

Random current testing for CMOS logic circuits by monitoring a dynamic power supply current

New design error modeling and metrics for design validation

Locating logic design errors via test generation and don't-care propagation

Information modelling of folded and unfolded design

On modeling integrated design environments

SEESIM-a fast synchronous sequential circuit fault simulator with single event equivalence

Linear time fault simulation algorithm using a content addressable memory

Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up

SPADES: a simulator for path delay faults in sequential circuits

A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation

An exact analytic technique for simulating uniform RC lines

A fast and accurate characterization method for full-CMOS circuits

SYNTEST: an environment for system-level design for test

Harmonic scheduling of linear recurrences for digital filter design

Generating pipelined datapaths using reduction techniques to shorten critical paths

Design for testability view on placement and routing

A time optimal robust path-delay-fault self-testable adder

A performance driven generator for efficient testable conditional-sum-adders

Topology optimization techniques for power/ground networks in VLSI

Crossing distribution (circuit layout CAD)

An optimal channel pin assignment with multiple intervals for building block layout

A neural network based algorithm for the scheduling problem in high-level synthesis

Heuristics for branch-and-bound global attraction

Automatic module allocation in high level synthesis

Automatic partitioning for deterministic test

MILEF: an efficient approach to mixed level automatic test pattern generation

Generation of deterministic test patterns by minimal basic test sets

Cross-fertilizing FSM verification techniques and sequential diagnosis

A distributed routing system for multilayer SOG

A fast multilayer general area router for MCM designs

Routing algorithms for multi-chip modules

Minimal area merger of finite state machine controllers

ROM-based finite state machines with PLA address modifiers

Efficient constrained encoding for VLSI sequential logic synthesis

A multilevel testability assistant for VLSI design

Tackling cost optimization in testable design by forward inferencing

SIESTA: a multi-facet scan design system

Towards a requirements definition, specification and system design environment

A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping

Maximal reduction of lookup-table based FPGAs

Chip assembly in the PLAYOUT VLSI design system

Embedded pin assignment for top down system design

On the intrinsic Rent parameter and spectra-based partitioning methodologies

Application-specific microelectronics for mechatronic systems

High-level synthesis in a rapid-prototype environment for mechatronic systems

Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions

ALU synthesis from HDL descriptions to optimized multi-level logic

Boolean matching in logic synthesis

P.Size: a sizing aid for optimized designs

PERFLEX: a performance driven module generator

An efficient methodology for symbolic compaction of analog ICs with multiple symmetry constraints

Delay macromodels for the timing analysis of GaAs DCFL

DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits

The exact solution of timing verification

Transient simulation of lossy coupled transmission lines

Performance-driven interconnection optimization for microarchitecture synthesis

Flexible controlpath microarchitecture synthesis based on artificial intelligence

An integer programming approach to instruction implementation method selection problem

Verification of digital circuits based on formal semantics of a hardware description language

State machine abstraction from circuit layouts using BDDs: applications in verification and synthesis

Design verification considering manufacturing tolerances by using worst-case distances

Correctness verification of concurrent controller specifications

Combined topological and functionality based delay estimation using at layout-driven approach for high level applications

System clock estimation based on clock slack minimization

Timing models for high-level synthesis

A genetic algorithm for macro cell placement

Wolverines: standard cell placement on a network of workstations

Parallel algorithms for slicing based final placement

Communication based logic partitioning

Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation

DESB, a functional abstractor for CMOS VLSI circuits

Design of delay insensitive circuits using multi-ring structures

Asynchronous state machine synthesis using data driven clocks

Path Breaker: a tool for the optimal design of speed independent asynchronous controllers

EURO-DAC '92. European Design Automation Conference, EURO-VHDL '92 (Cat. No.92CH3126-0)

Design assistance for CAD frameworks

Unifying tool, data and process flow management

ANT-A test harness for the NELSIS CAD system

Finite state machine verification on MIMD machines

An approach to multi-paradigm controller synthesis from timing diagram specifications

Cellular scan test generation for sequential circuits

Experiments on the synthesis and testability of non-scan finite state machines

A quantitative measure of robustness for delay fault testing

JESSI common framework design management-the means to configuration and execution of the design process

Design of a tool interface for integrated CAD-environments

Representing the hardware design process by a common data schema

GOSSIP-a generic system for statistical circuit design

A generic software system for drift reliability optimization of VLSI circuits

PAR-APLAC: parallel circuit analysis and optimization

Design technology research for the nineties: more of the same?

Challenges for CAD in computer development in the 1990s

Electronic systems design-tools and methodology to meet the productivity change

Compiling VHDL into a high-level synthesis design representation

Flexible timing specification in a VHDL synthesis subset

Semantics and synthesis of signals in behavioral VHDL

Integration of SDL and VHDL for high-level digital design

Using VHDL for simulation of SDL specifications

VHDL and fuzzy logic if-then rules

Experiences and issues in VHDL-based synthesis

VHDL for high speed desktop video ICs-experience with replacement of other simulator

Proceedings of the European Design Automation Conference, 1990., EDAC.

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