NDLI: Testable path delay fault cover for sequential circuits

Content Provider	IEEE Xplore Digital Library
Author	Krstic, A. Chakradhar, S.T. Kwang-Ting Cheng
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA (Krstic, A.)
Abstract	We present an algorithm for identifying a set of faults that do not have to be targeted by a sequential delay test generator. These faults either cannot independently affect the performance of the circuit or no test can be generated for them. To find such faults, our methodology takes advantage of the sequential behavior of the circuit as well as of the information about uncontrollable signals in the sequential circuit. It can handle sequential circuits described as two- or multi-level netlists. The outcome of applying our methodology is reduced delay test generation effort and smaller test set. We present experimental results on several ISCAS 89 benchmark circuits demonstrating that a large number of path delay faults in these circuits either cannot or does not have to be examined for delay defects.
Starting Page	220
Ending Page	226
File Size	813115
Page Count	7
File Format	PDF
ISBN	081867573X
DOI	10.1109/EURDAC.1996.558208
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-09-16
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Sequential analysis Delay Circuit faults Sequential circuits Combinational circuits Fault diagnosis Electrical fault detection Fault detection Manufacturing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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