NDLI: Use of embedded scheduling to compile VHDL for effective parallel simulation

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Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition

Proceedings of EURO-DAC. European Design Automation Conference

Proceedings of EURO-DAC. European Design Automation Conference

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Use of embedded scheduling to compile VHDL for effective parallel simulation

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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

Proceedings EURO-DAC '92: European Design Automation Conference

Proceedings of the European Design Automation Conference, 1990., EDAC.

Use of embedded scheduling to compile VHDL for effective parallel simulation

Content Provider	IEEE Xplore Digital Library
Author	Willis, J. Zhiyuan Li Tsang-Puu Lin
Copyright Year	1995
Description	Author affiliation: Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA (Willis, J.)
Abstract	This paper describes VHDL compilation techniques, embodied in the Auriga compiler, which facilitate parallel or distributed simulation by embedding evaluation scheduling in the emitted code. Unlike earlier but related cycle-driven techniques which map VHDL into simpler temporal semantics, the techniques described here preserve VHDL's full temporal semantics. Experimental results indicate effective simulation acceleration using as many as 16 processors. Ongoing work involves evaluation with much larger models and machine configurations.
Starting Page	400
Ending Page	405
File Size	612475
Page Count	6
File Format	PDF
ISBN	0818671564
DOI	10.1109/EURDAC.1995.527436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-09-18
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Yarn Processor scheduling Computational modeling Runtime Kernel Context modeling Scheduling algorithm Signal processing Data structures Contracts
Content Type	Text
Resource Type	Article

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