NDLI: Energy efficient joint scheduling and multi-core interconnect design

Content Provider	IEEE Xplore Digital Library
Author	Xu, C.Q. Xue, C.J. Yi He Sha, E.H.M.
Copyright Year	2010
Description	Author affiliation: Dept. of CS, City Univ. of Hong Kong, China (Xue, C.J.) \|\| Dept. of CS, Univ. of Texas at Dallas, Richardson, 75080, USA (Xu, C.Q.; Yi He; Sha, E.H.M.)
Abstract	Energy efficient and high performance interconnect is critical for multi-core architecture. Interconnect with power saving segmented buses satisfies the tight latency and high volumn data transfer needs of applications with large embeded pallelism. This paper analyzes the major energy consumption factors of interconnect with segmented buses from high level synthesis. It presents a computation and inter-core data transfer scheduling algorithm to minimize the interconnect energy consumption by addressing the analyzed factors while exploring an application's maximum parallelism. This paper jointly considers scheduling and interconnect design. It presents an application specific approach to determine the minimum number of segmented buses required and an optimal inter core data transfer schedule which can be used to configure the switches on the segmented buses to avoid bus contention and minimize interconnect energy consumption with a given application. Experimental results show that the proposed scheduling algorithm can reduce interconnect dynamic about 23% on average compared to the other communication cost conscious scheduling techniques for evaluated high parallelism DSP applications.
Starting Page	879
Ending Page	884
File Size	550807
Page Count	6
File Format	PDF
ISBN	9781424457656
DOI	10.1109/ASPDAC.2010.5419678
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-01-18
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy efficiency Energy consumption Scheduling algorithm Parallel processing Computer architecture Delay High level synthesis Concurrent computing Algorithm design and analysis Processor scheduling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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