NDLI: Degree-of-freedom analysis for sequential machines targeting BIST quality and gate area

Content Provider	IEEE Xplore Digital Library
Author	Roy, S. Sikdar, B.K. Mukherjee, M. Das, D.K.
Copyright Year	2002
Description	Author affiliation: Dept. of Comput. Sci. & Technol., Kalyani Govt. Eng. Coll., India (Roy, S.)
Abstract	This paper reports the design of BIST structures for sequential machines. Testability of an FSM is limited due to the fact that some machine states remain unreachable and some act as a sink under any input sequence. The proposed scheme provides uniform mobility, referred to as degree of freedom, among the machine states in test mode by enhancing the reachability and emitability of the states. Uniform mobility of states ensures higher fault efficiency in a BIST structure. A graph based approach is introduced for state code assignment to minimize gate area. Experimental results on benchmark circuits establish that the proposed scheme does improve the BIST quality simultaneously reducing the gate area of the synthesized machine.
Sponsorship	VLSI Soc. India (VSI)
Starting Page	671
Ending Page	676
File Size	470024
Page Count	6
File Format	PDF
ISBN	0769514413
DOI	10.1109/ASPDAC.2002.995012
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Built-in self-test Circuit testing Sequential circuits Circuit faults Sequential analysis Test pattern generators Computer science Design engineering Circuit synthesis Educational institutions
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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