NDLI: A hardware simulation engine based on decision diagrams

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A hardware simulation engine based on decision diagrams

Content Provider	IEEE Xplore Digital Library
Author	Iguchi, Y. Matsuura, M. Sasao, T. Iseno, A.
Copyright Year	2000
Description	Author affiliation: Dept. of Comput. Sci., Meiji Univ., Kawasaki, Japan (Iguchi, Y.)
Abstract	A hardware logic simulation engine based on decision diagrams is presented. For the data structure of the engine, we propose PMDDs (Paged reduced ordered Multi-valued Decision Diagrams). A unit of this engine consists of memory (RAMs) and control circuits: RAMs store the PMDD data, and the control circuits trace the edges according to the input vectors. The engine consists of several units, and is accelerated by pipelining. Experimental results using a prototype are shown.
Starting Page	73
Ending Page	76
File Size	394040
Page Count	4
File Format	PDF
ISBN	0780359739
DOI	10.1109/ASPDAC.2000.835073
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-01-25
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Engines Binary decision diagrams Computational modeling Circuit simulation Logic Computer simulation Computer science Data structures Boolean functions
Content Type	Text
Resource Type	Article

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