NDLI: Secure Scan Design with Dynamically Configurable Connection

Content Provider	IEEE Xplore Digital Library
Author	Atobe, Y. Youhua Shi Yanagisawa, M. Togawa, N.
Copyright Year	2013
Abstract	Scan test is a powerful test technique which can control and observe the internal states of the circuit under test through scan chains. However, it has been reported that it's possible to retrieve secret keys from cryptographic LSIs through scan chains. Therefore new secure test methods are required to satisfy both testability and security requirements. In this paper, a secure scan design is proposed to achieve adequate security requirement as a countermeasure against scan-based attacks, while still maintain high testability like normal scan testing. In our method, the internal scan chain is divided into several sub chains, and the connection order of sub chains can be dynamically changed. In addition, how to decide the connection order of those sub chains so that it can't be identified by an attacker is also proposed in this paper. The proposed method is implemented on an AES circuit to show its effectiveness, and a security analysis is also given to show how the proposed approach can be used as a countermeasure against those known scan-based attacks.
Sponsorship	IEEE Comput. Soc.
Starting Page	256
Ending Page	262
File Size	325565
Page Count	7
File Format	PDF
ISBN	9780769551302
DOI	10.1109/PRDC.2013.47
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-12-02
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Cryptography Registers Manufacturing Latches Testing Vectors AES scan chain scan-based attack secure scan design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Dynamically changeable secure scan architecture against scan-based side channel attack

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures

AES design space exploration new line for scan attack resiliency

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

A Scan-Based Attack Based on Discriminators for AES Cryptosystems

Differential scan-path: A novel solution for secure design-for-testability

Scan-based attack against DES cryptosystems using scan signatures

New scan-based attack using only the test mode

VLSI Implementation of Robust Secure Scan Based Design for Differential Cryptanalaysis

Secure Scan Design with Dynamically Configurable Connection

Similar Documents

Dynamically changeable secure scan architecture against scan-based side channel attack

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures

AES design space exploration new line for scan attack resiliency

State dependent scan flip-flop with key-based configuration against scan-based side channel attack on RSA circuit

A Scan-Based Attack Based on Discriminators for AES Cryptosystems

Differential scan-path: A novel solution for secure design-for-testability

Scan-based attack against DES cryptosystems using scan signatures

New scan-based attack using only the test mode

VLSI Implementation of Robust Secure Scan Based Design for Differential Cryptanalaysis

Secure Scan Design with Dynamically Configurable Connection