NDLI: A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

Content Provider	IEEE Xplore Digital Library
Author	In-Seok Jung Yong-Bin Kim
Copyright Year	2014
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA (In-Seok Jung; Yong-Bin Kim)
Abstract	This paper presents a low-power 12-bit 32MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a single input with a novel Built-in Self Calibration (BiSC) feature to reduce the capacitor mismatch of the digital-to-analog converter (DAC) and to compensate the comparator input offset voltage. The proposed self-calibration scheme optimize the mismatch of the DAC by changing additional auxiliary capacitor array during calibration mode. In addition, in order to minimize the offset voltage of the comparator in the SAR ADC, a simplified voltage amplifier is proposed. The controller for the proposed algorithm operates as fore-ground operation so that low power consumption is achieved. Consequently, the mismatch error of the DAC can be minimized and the SAR based ADC operates without any extra power dissipation for the circuitry of self calibration during normal operation. The prototype was designed using 0.13μm single poly 6 metal standard CMOS technology. The ADC achieves a SNDR of 65.2 dB and consumes 3.57 mW with 1.2V supply voltage and sampling rate of 32 MS/s. Compared to the converters that use the conventional procedure, INL and DNL are reduced by about 45% and 51%, respectively.
Starting Page	276
Ending Page	280
File Size	162819
Page Count	5
File Format	PDF
e-ISBN	9781479961559
DOI	10.1109/DFT.2014.6962078
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-10-01
Publisher Place	Netherlands
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Calibration Capacitors Power demand Capacitance Arrays Very large scale integration Registers
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Novel Built-in Self Calibration Technique To Minimize Capacitor Mismatch for 12-bit 32 MS / s SAR ADC

A novel self-calibration scheme for 12-bit 50MS/s SAR ADC

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs

A mutual characterization based SAR ADC self-testing technique

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

A 12-bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array

Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction

Digital self-calibration technique based on 14-bit SAR ADC

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch

Similar Documents

A Novel Built-in Self Calibration Technique To Minimize Capacitor Mismatch for 12-bit 32 MS / s SAR ADC

A novel self-calibration scheme for 12-bit 50MS/s SAR ADC

A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique

Parasitic calibration by two-step ratio approaching technique for split capacitor array SAR ADCs

A mutual characterization based SAR ADC self-testing technique

Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

A 12-bit 200KS/s SAR ADC with a mixed switching scheme and integer-based split capacitor array

Testing and Calibration of SAR ADCs by MCT-Based Bit Weight Extraction

Digital self-calibration technique based on 14-bit SAR ADC

A 12-bit 32MS/s SAR ADC using built-in self calibration technique to minimize capacitor mismatch