NDLI: Design of radiation tolerant CMOS APS system-on-a-chip image sensors

Content Provider	IEEE Xplore Digital Library
Author	Eid, E.-S. Ay, S.U. Fossum, E.R.
Copyright Year	2002
Description	Author affiliation: Photobit Technol. Corp., Pasadena, CA, USA (Eid, E.-S.; Ay, S.U.; Fossum, E.R.)
Abstract	A methodology for designing radiation tolerant CMOS APS SOC image sensors is presented. It is based on the experimental results of test chips that had been designed, fabricated, and characterized. Details of the basic building blocks of a proposed design are presented. The proposed design is in a 0.35-/spl mu/m CMOS standard process. The radiation tolerance level could be up to 30 Mrad (Si) total dose of ionizing radiation. The proposed methodology has the potential of yielding highly integrated, highly functional, highly compact, low power, radiation tolerant, cost effective CMOS APS SOC image sensors.
Sponsorship	IEEE Aerosp. & Electron. Syst. Soc
Starting Page	4
Ending Page	4
File Size	1112557
Page Count	1
File Format	PDF
ISBN	078037231X
DOI	10.1109/AERO.2002.1036912
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-03-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS image sensors Image sensors CMOS technology Space technology System-on-a-chip CMOS process Integrated circuit technology CMOS digital integrated circuits CMOS analog integrated circuits Charge coupled devices
Content Type	Text
Resource Type	Article

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Design of radiation tolerant CMOS APS system-on-a-chip image sensors