NDLI: Low-latency asynchronous FIFO buffers

Content Provider	IEEE Xplore Digital Library
Author	Yantchev, J.T. Huang, C.G. Josephs, M.B. Nedelchev, I.M.
Copyright Year	1995
Description	Author affiliation: Dept. of Comput. Sci., Adelaide Univ., SA, Australia (Yantchev, J.T.)
Abstract	A parallel asynchronous implementation of a FIFO buffer is described and compared with the conventional alternative asynchronous implementation, Sutherland's micropipeline. The parallel design has the potential for significant reductions in propagation delay at the cost of insignificant increases in cycle-time (i.e. reduced throughput) and area. Although in certain applications, e.g. DSP, only high throughput may be important, in others, e.g. packet switching, throughout and propagation delay both matter. We consider the parallel design to be most useful as part of the interface circuitry required by devices that asynchronously exchange data in bursts over inter-chip communication wires and use a single acknowledge signal for each burst of data. In particular, a high-throughput multiple-burst signalling scheme is supported, in which a second burst of data is transmitted at the same time as the previous burst is acknowledged, effectively increasing the overall throughput.
Starting Page	24
Ending Page	31
File Size	622805
Page Count	8
File Format	PDF
ISBN	0818670983
DOI	10.1109/WCADM.1995.514639
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-05-30
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Packet switching Pipelines Buffer storage Switches Propagation delay Computer science Very large scale integration Costs Digital signal processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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