NDLI: Continuous optimization

Content Provider	IEEE Xplore Digital Library
Author	Fahs, B. Rafacz, T. Patel, S.J. Lumetta, S.S.
Copyright Year	2005
Description	Author affiliation: Center for Reliable & High Performance Comput., Illinois Univ. at Urbana-Champaign, IL, USA (Fahs, B.; Rafacz, T.; Patel, S.J.; Lumetta, S.S.)
Abstract	This paper presents a hardware-based dynamic optimizer that continuously optimizes an application's instruction stream. In continuous optimization, dataflow optimizations are performed using simple, table-based hardware placed in the rename stage of the processor pipeline. The continuous optimizer reduces dataflow height by performing constant propagation, reassociation, redundant load elimination, store forwarding, and silent store removal. To enhance the impact of the optimizations, the optimizer integrates values generated by the execution units back into the optimization process. Continuous optimization allows instructions with input values known at optimization time to be executed in the optimizer, leaving less work for the out-of-order portion of the pipeline. Continuous optimization can detect branch mispredictions earlier and thus reduce the misprediction penalty. In this paper, we present a detailed description of a hardware optimizer and evaluate it in the context of a contemporary microarchitecture running current workloads. Our analysis of SPECint, SPECfp, and mediabench workloads reveals that a hardware optimizer can directly execute 33% of instructions, resolve 29% of mispredicted branches, and generate addresses for 76% of memory operations. These positive effects combine to provide speed ups in the range 0.99 to 1.27.
Sponsorship	IEEE Comput. Soc. Tech. Comm. on Comput. Archit. ACM SIGARCH
Starting Page	86
Ending Page	97
File Size	233530
Page Count	12
File Format	PDF
ISBN	076952270X
ISSN	10636897
DOI	10.1109/ISCA.2005.19
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-06-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Pipelines Optimizing compilers Registers High performance computing Out of order Microarchitecture Uninterruptible power systems Program processors Decoding
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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