NDLI: Cache decay: exploiting generational behavior to reduce cache leakage power

Content Provider	IEEE Xplore Digital Library
Author	Kaxiras, S. Zhigang Hu Martonosi, M.
Copyright Year	2001
Abstract	Power dissipation is increasingly important in CPUs ranging from those intended for mobile use, all the way up to high performance processors for high-end servers. While the bulk of the power dissipated is dynamic switching power leakage power is also beginning to be a concern. Chipmakers expect that in future chip generations, leakage's proportion of total chip power will increase significantly. This paper examines methods for reducing leakage power within the cache memories of the CPU. Because caches comprise much of a CPU chip's area and transistor counts, they are reasonable targets for attacking leakage. We discuss policies and implementations for reducing cache leakage by invalidating and "turning off" cache lines when they hold data not likely to be reused. In particular our approach is targeted at the generational nature of cache line usage. That is, cache lines typically have a flurry of frequent use when first brought into the cache, and then have a period of "dead time" before they are evicted. By devising effective, low-power ways of deducing dead time, our results show that in many cases we can reduce Ll cache leakage energy by 4/spl times/ in SPEC2000 applications without impacting performance. Because our decay-based techniques have notions of competitive on-line algorithms at their roots, their energy usage can be theoretically bounded at within a factor of two of the optimal oracle-based policy. We also examine adaptive decay-based policies that make energy-minimizing policy choices on a per-application basis by choosing appropriate decay intervals individually, for each cache line. Our proposed adaptive policies effectively reduce Ll cache leakage energy by 5/spl times/ for the SPEC2000 with only negligible degradations in performance.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Archit.
Starting Page	240
Ending Page	251
File Size	381416
Page Count	12
File Format	PDF
ISBN	0769511627
ISSN	10636897
DOI	10.1109/ISCA.2001.937453
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-06-30
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power generation Power dissipation Turning Central Processing Unit Leakage current Circuits and systems Cache memory Thermal degradation Pressing Energy management
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power (2001)

Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power

Cache decay: exploiting generational behavior to reduce cache leakage power

Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power (2001)

Cache Decay: Exploiting Generational Behavior (2001)

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