NDLI: A graph-based silicon compiler for concurrent VLSI systems

Content Provider	IEEE Xplore Digital Library
Author	Bergamaschi, R. Allerton, D.J.
Copyright Year	1988
Description	Author affiliation: Dept. of Electron. & Comput. Sci., Southampton Univ., UK (Bergamaschi, R.; Allerton, D.J.)
Abstract	A silicon compiler able to synthesize concurrent VLSI systems is described. This compiler differs from most existing silicon compilers as there is no target architecture, and yet results have shown that it performs reasonably well for a range of applications. It features a novel technique for control-step partitioning based on a precedence graph. Concurrency is detected and extracted from the input description in order to generate a fast implementation. The graph, which corresponds to a state diagram of the circuit, is further optimized using a simple rule-based approach. A controller able to control any number of concurrent processes, based on a synchronous token-passing mechanism, is generated. Control signals are submitted to two-level and multilevel logic minimization, and they can be implemented either as a programmable logic arrays (PLA) or with standard cells. The data path is generated as a netlist of technology-independent parameterized cells which are mapped into cells from a library by a module binder. The final layout is automatically generated by placement-and-routing programs.<>
Starting Page	36
Ending Page	47
File Size	668697
Page Count	12
File Format	PDF
ISBN	081860834X
DOI	10.1109/CMPEUR.1988.4932
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1988-04-11
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon compiler Very large scale integration Programmable logic arrays Programmable control Control system synthesis Concurrent computing Circuits Synchronous generators Minimization Libraries
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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