NDLI: A CMOS low-voltage fully differential sample-and-hold circuit

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2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

2012 IEEE Asia Pacific Conference on Circuits and Systems

2010 IEEE Asia Pacific Conference on Circuits and Systems

APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems

Technical program

New architectures for low-power delta-sigma analog-to-digital converter

Body channel communication for low energy BSN/BAN

High-performance data converters: Trends, process technologies and design challenges

A low offset rail-to-rail 12b 2MS/s 0.18μm CMOS cyclic ADC

A 1.8V 12-bit 230-MS/s pipeline ADC in 0.18μm CMOS technology

A flexible 12-bit self-calibrated quad-core current-steering DAC

Reconfigurable baseband processing platform for communication systems

Enhanced channel selection using digital low-IF in Weaver receiver architecture

Mapping algorithms of MIMO to a Multi-Pipeline Reconfigurable System

Scalable interpolation architecture for soft-decision Reed-Solomon decoding

Flexible LDPC decoder architecture for high-throughput applications

Cumulative electrostatic discharge induced degradation of power-rail ESD clamp device in high-voltage CMOS/DMOS technologies

UVeriESD: An ESD verification tool for SoC design

Active ESD protection design against cross-power-domain ESD stresses in CMOS integrated circuits

Measurement on snapback holding voltage of high-voltage LDMOS for latch-up consideration

A vision sensor with background subtraction processor using mixed analog-digital architecture

PCA/ICA-based SVM for fall recognition using MEMS motion sensing data

A low-power RF front-end of passive UHF RFID transponders

PSoC implementing vehicle auxiliary vacuum brake system with Kalman filter

A simple and ultra-low power capacitive pressure micro-sensor sensing system design

Q-band bandpass filter designs in heterodyne receiver for radio astronomy

Multi-spurious suppression for microstrip dual-mode bandpass filter using triple U-shaped defected ground structure

Compact microstrip square-loop dual-mode bandpass filter design with wideband response

Experimental investigation of the operation characteristics of 3-phase 3-wire active power filter

Study on assessment model of event-type power disturbances

Research on harmonic penetration between different voltage levels

A decoupling-controlled STATCOM for power quality improvement of impact loads

A 0.6-V 1.8-μW automatic gain control circuit for digital hearing aid

A low-power bio-sensor interface with wide measurement range

An efficiency-enhanced CMOS voltage regulator module for bio-electronic implants

Patient classification based on pre-hospital heart rate variability

Retinal vessel segmentation using histogram matching

1.5-V 10-Ms/s 8-bit Pipeline ADC in 0.13 μm CMOS using metal fringe capacitor

A low power 12-bit 40MS/s pipelined ADC with digital calibration

A two-stage pipelined passive charge-sharing SAR ADC

A 12-bit 150-MSample/s current-steering DAC

A new wideband, high-linear passive Sample and Hold structure suitable for high-speed, high-resolution ADCs

A 1V low noise amplifier for WiMAX / UWB applications

Signal-to-noise ratio improvement of common-gate CMOS LNA for Ultra-Wide-Band

A 3–5GHz amplitude and spectrum tunable impulse radio UWB transmitter

A 480 Mbps MB-OFDM-based UWB baseband inner transceiver

Area-time-power efficient VLSI design for residue-to-binary converter based on moduli set $(2^{n},2^{n+1}−1,2^{n}−1)$

Design of square generator with small look-up table

High-speed and low-power serial accumulator for serial/parallel multiplier

Low-latency VLSI architecture of a 3-input floating-point adder

Fast point operation architecture for Elliptic Curve Cryptography

A new family of robust sequential partial update least mean M-estimate adaptive filtering algorithms

Mean square error analysis of the PG algorithm for adaptive IIR notch filter with constrained poles and zeros using power spectral density method

A new noise-constrained normalized least mean squares adaptive filtering algorithm

A variable parameter improved proportionate normalized LMS algorithm

On the convergence analysis of the transform domain normalized LMS and related M-estimate algorithms

Fractional Fourier transform based auditory feature for language identification

Modified quadratic discrimination function for non-normal distribution and its application in speech emotion recognition

Gesture recognition based on 3D accelerometer for cell phones interaction

Channel compensation technology in differential GSV-SVM speaker verification system

Cluster validation for subspace clustering on high dimensional data

Nonlinear decoupled control of back-to-back voltage source converter

Evaluation of disaster level caused by power quality problems

An optimal control strategy for power capacity based on railway power static conditioner

Dynamic secondary arc analysis and simulation research under different line model

Power saving mobile monitoring system on architectures

An ANT network bi-directional wireless homecare system

Automatic ECG interpretation via morphological feature extraction and SVM inference nets

Modeling malware propagation in complex networks based on cellular automata

A mobile intelligent sphygmogram analyzer

SAR ADC algorithm with redundancy

A low kick back noise latched comparator for high speed folding and interpolating ADC

A pseudo-differential comparator-based pipelined ADC with common mode feedforward technique

An ultra-low-power sensor interface built around a reconfigurable incremental sigma-delta modulator for sensor networks employing electromagnetic backscatter

An ultra low-power Successive Approximation ADC using an offset-biased auto-zero comparator

A 0.13μm CMOS UWB receiver front-end using passive mixer

A 18.9dB conversion gain folded mixer for WiMAX system

New architecture for envelope-tracking power amplifier for base station

60 GHz 130-nm CMOS second harmonic power amplifiers

A concurrent dual-band mixer with on-wafer balun for multi-standard applications

A novel pipeline architecture for H.264/AVC CABAC decoder

A high throughput in-loop de-blocking filter supporting H.264/AVC BP/MP/HP video coding

Area and throughput trade-offs in design of arithmetic encoder for JPEG2000

A new VLSI 2-D diagonal-symmetry filter architecture design

Improving the design of parallel-pipeline cyclic decoders towards fault-secure versions

A personal identification method based on finger’s outline

Super-resolution image by curve fitting in the threshold decomposition domain

A new iterative reconstruction scheme for signal reconstruction

Short response Hilbert transform for edge detection

Energy efficient lossless image compression with prediction-based transform

Multi-Vth FinFET sequential circuits with independent-gate bias and work-function engineering for reduced power consumption

A new statistical timing analyzer propagating delay and slew distributions simultaneously

A design method for skew tolerant latch design

Nanoholes microscopy

Stochastic estimation trip frequency of sensitive equipment due to voltage sag

Support vector machines based on Lyapunov exponents in power load forecasting model

Overview of radiation effects and design constraints off fully custom SMPS

Adjustable low consumption circuit for monitorization of power source voltages in a SoC

Recurrent type ANFIS using local search technique for time series prediction

An extreme learning machine approach for training Time Variant Neural Networks

An efficient Elastic Net method for edge linking of images

Design of CNN cell with low-power variable-gm OTA and its application

A novel CMOS switched-current mode sequential shift forward inference circuit for fuzzy logic controller

A Li-ion battery charging design for biomedical implants

Architecture for Heart Rate measurement

A novel current-mode readout circuit for ISFET sensor

A 1V CMOS active pixel sensor with enhanced dynamic range

A novel WSN based intelligent training system for children’s sensory integration

A low jitter DLL-based pulsewidth control loop with wide duty cycle adjustment

Space-time multiuser detection with alternating soft interference cancellation in highly loaded CDMA systems

Design of variable fractional-delay 2-D FIR digital filters by weighted least-squares approach

Real-time implementation of Wave Field Synthesis for sound reproduction systems

A robust iterative inverse filtering approach for speech dereverberation in presence of disturbances

An integrative algorithm for predicting protein coding regions

Cordic architecture for Hough Transform applications

Adaptive intra mode bit skip in intra coding

Radar echo envelope extraction using Teager energy operator and wavelet transform

An application of DSP to automatic PMD compensation in optical fiber communication systems

High-performance floating-point VLSI architecture of lifting-based forward and inverse wavelet transforms

Design of discrete coefficient frequency-response-masking FIR digital filters

Digital signal processing in electrical capacitance tomography

Stability analysis of a generalised 2D digital Roesser type systems via lagrange method

Single-channel blind separation of Two QPSK signals using per-survivor processing

A newly high-speed equalizer for QAM signals

Blind MIMO direct chaotic communication system identification via higher-order statistic

A decision-directed receiver for CDMA MIMO systems over multipath fading channel

Power plant construction project safety management evaluation with fuzzy neural network model

A new method of multichannel loudness compensation for hearing aids

DTCWT-based dynamic texture features for visual speech recognition

Curved segmentation path generation for unconstrained handwritten Chinese text lines

An IA-Brush interactive painting system

VoIP frame bundling for WiMAX downlink

Efficient bit-rate estimation technique for CABAC

A new image coding quality assessment

Efficient pre-clipping and clipping algorithms for 3D graphics geometry computation

Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop

Low-quiescent-current fast-response current-feedback shunt regulator

Li-ion battery management chip for multi-cell battery pack

A design of CMOS bandgap reference with low thermal drift and low offset

On the design of a power conversion circuit

A CMOS 434/868 MHz FSK/OOK transmitter with integrated fractional-N PLL

5 GHz phase locked loop with auto band selection

A 25-GHz differential LC-VCO in 90-nm CMOS

A 5GHz wide tuning range LC-VCO in sub-micrometer CMOS technology

SSTA considering switching process induced correlations

Interconnect thermal simulation with higher order spatial accuracy

A novel leakage-estimation method for input-vector control

Three-level AND-OR-XOR network synthesis: A GA based approach

HW/SW co-simulation platforms for VLSI design

Frequency synchronization for OFDM systems over doubly-selective channels

SDR Based Multi-Mode DBF for micro-satellite SAR

Transmit/Receive beamformer design and resource allocation in multiuser MIMO-OFDM systems

Localization and time synchronization in wireless sensor networks: A unified approach

A cross decision feedback gsc-based capon multiuser receiver for space-time block coded CDMA systems

Parallel visualization of multiple translucent isosurfaces

GPU accelerated fast FEM deformation simulation

Image spatial diffusion on GPUs

Real-time simulation of large-scale dynamic forest with GPU

Emerging technology about GPGPU

Locating observers and controllers for severely disturbed power system using mode matrices

Field experiments of wide area damping controllers for multiple HVDC links

Power system transient instability detection algorithm based on real time measurement

Fast assessment of regional voltage stability based on WAMS

PMU standard of China

A very-high output impedance current mirror for very-low voltage biomedical analog circuits

A moving binary search SAR-ADC for low power biomedical data acquisition system

Low power integrated circuits for wireless neural recording applications

Function-based memory partitioning on low power digital signal processor for cochlear implants

Microelectronic channel bridge and signal regeneration of injured spinal cords

A low supply-dependence fully-MOSFET voltage reference for low-voltage and low-power

A sub-1 volt CMOS bandgap reference with high power supply rejection

A topological comparison of PWM and hysteresis controls in switching audio amplifiers

A high performance peak detector sample and hold circuit for detecting power supply noise

Design of a 1.8V on-chip voltage generator for applications in low voltage transceiver

A 1.25Gbps all-digital clock and data recovery circuit with binary frequency acquisition

A 10-Gb/s fully balanced differential output transimpedance amplifier in 0.18-μm CMOS technology for SDH/SONET application

A 5Gb/s adaptive equalizer using filter switching

A 1.0 volt thermal noise-canceling CMOS transimpedance-based amplifier

Design and implementation of the configuration circuit for FDP FPGA

FIR filter design on Flexible Engine/Generic ALU array and its dedicated synthesis algorithm

Dynamically reconfigurable architecture for multi-rate compatible regular LDPC decoding

An FPGA implementation of a DWT with 5/3 filter using semi-programmable hardware

A reconfigurable arbiter for SOC applications

Arithmetic reduction of adder leakage in nanoscale CMOS

A novel configurable no dead-zone digital phase detector design

A high speed single photon counting module

A low-power area-efficient SRAM with enhanced read stability in 0.18-μm CMOS

FPGA-based embedded system design

Configuration representation of a link-type self-reconfigurable mobile robot

Intelligent human-machine cooperative robot for orthopaedic surgery

Inverse dynamics of 3-RRRT parallel manipulator

Decreasing end-effector deformation of the flexible manipulator through local motion planning

Experimental studies on a micromanipulator for micro/nano manipulation

Analysis of time delay effects on wide area damping control

Determination of wide-area PSS locations and feedback signals using improved residue matrices

Interface control based on power flow tracing and generator re-dispatching

A novel inter-area oscillation damping design based on wide area measurements

WAMS based dynamic state estimator during power system transient process

Array blind calibration criterions for low-angle tracking

Variable step-size speech blind separation employing Laplacian normal mixture distribution model

Throughput analysise of cooperative multiple packet reception based on NDMA

Adaptive blind equalization of SIMO FIR second order Volterra channels

Non-negative matrix factorization for images with Laplacian noise

An untrimmed CMOS amplifier with high CMRR and low offset for sensor applications

A nonlinearity error calibration technique based on an opamp distortion modeling

Highly-linear CMOS OTA with compensation of mobility reduction

An improved source follower with wide swing and low output impedance

A low power consumption, high speed Op-amp for a 10-bit 100MSPS parallel pipeline ADC

Optimal power allocation for channel estimation in MIMO-OFCDM systems

A new M-estimator for performance analysis of cellular digital mobile radio systems including diversity technique

Gram-Schmidt-based QR decomposition for MIMO detection: VLSI implementation and comparison

A high performance four-parallel 128/64-point $radix-2^{4}$ FFT/IFFT processor for MIMO-OFDM systems

Low power multiplexer tree design using dynamic propagation path control

Body-bootstrapped-buffer circuit for CMOS static power reduction

A power-gating scheme for CAL circuits using single-phase power-clock

An all digital spread spectrum clock generator with programmable spread ratio for SoC applications

Cycle-time-aware sequential way-access set-associative cache for low energy consumption

Design of fractional delay FIR filter using discrete cosine transform

Design of IIR fractional differentiator With Peano kernel

Unconstrained IIR filter design method using argument principle based stability criterion

A realization of digital filter banks for reconstruction of uniformly sampled signals from nonuniform samples

A novel structure for 2nd order digital filters

Efficient IFFT design using mapping method

40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications

Adaptive Cholesky based MMSE equalizer in GSM

Hardware efficient frequency estimator based on data-aided algorithm for digital video broadcasting system

Skew variation compensating technique for clock mesh networks

Dynamic current limitation circuit for white LED driver

Design of single-inductor dual-output switching converters with average current mode control

Self-tuning PSM controller based on state machine

Optimizing the efficiency of DC-DC converters with an analog variable-frequency controller

High-resolution DPWM generator for digitally controlled DC-DC converters

Block-based belief propagation with in-place message updating for stereo vision

Omnidirection image restoration based on spherical perspective projection

Analysis of color space and similarity measure impact on stereo block matching

A virtual character recognition system based on optical detection of red light and its embedded implementation

A CDFG generating method from C program for LSI design

Genetical tuning of a capacitorless current-mode bandpass biquad based on single-stage CMOS OTA

Synthesis of optimal OTA-C filter structures with arbitrary transmission zeros via MINLP

Delta discrete-time operator-based doubly-terminated two-port: Application to filter design and stability testing

A cascadable current-mode universal biquadratic filter using MO-CCCCTAs

Multi-bandwidth analog filter design for SDR

Low energy CMOS true single phase power supply clocking adiabatic differential cascode voltage switch logic circuit

Single-phase power-gating adiabatic flip-flops

A CMOS adiabatic inverter operating with a single clock power supply to reduce non-adiabatic loss

Topology-related effects of Gated-Vdd and Gated-Vss techniques on full-adder leakage and delay at 65nm and 45 nm

A pipelined asynchronous 8051 soft-core implemented with Balsa

Design of sparse arrays with high sidelobe rejection

An FPGA architecture for real-time polyphase 2D FIR double-trapezoidal plane-wave filters

Recursive robust variable loading mvdr beamforming in impulsive noise environment

Efficient time varying frequency tracking using recursive estimation

Design of broadband beamformers for microphone arrays using variably-weighted least squares

Timing driven force-directed floorplanning with incremental static timing analyzer

Timing variation-aware high level synthesis: Current results and research challenges

A second-order gate delay modeling method with an efficient sensitivity analysis

Efficient cell characterization for SSTA

Incremental statistical static timing analysis with gate timing yield emphasis

A novel space vector modulation method of three-level inverter based on the synthesized middle space vectors

A capacitive-coupled transformerless active power filter with coupling current feedback control

Evaluation of quasi-resonant dc-link technique on generalized three-level inverter

Process simulation of Trench Gate and Plate and Trench Drain SOI NLIGBT with TCAD tools

CEERP: Cost-based Energy-Efficient Routing Protocol in wireless sensor networks

A RSSI-based environmental-adaptive dynamic radiation power management for Wireless Sensor Networks

Information accuracy versus jointly sensing nodes in wireless sensor networks

Study of mobile farmland information monitoring terminal based wireless data transmission technology

A 0.9–2.2GHz wide-band low-noise amplifier design

Current controlled fully balanced current conveyor

A switch IC implemented by four depletion-mode field effect transistors for dual-band GSM switch diplexer module

CDTA-based current limiters and applications

Low-voltage digitally controlled current differencing buffered amplifier

Low-jitter PLL by interpolate compensation

Frequency-invariant pattern synthesis for conformal array with space-time-polarization weighting

The design and algorithm mapping of a heterogeneous multi-core processor for SDR

Unambiguous tracking techniques for Galileo BOC(1,1) signals

Efficient modulation on the performance of coherent receivers for pseudo-chaotic TH-UWB system

Efficient radius and list updating units design for list sphere decoders

Electronic Shelf Label System based on public illuminating network

Robust solution for synchronous communication among multi clock domains

Efficient architecture for the Tate pairing in characteristic three

Study on a detection algorithm for MIMO systems

Traffic analysis of a mobile cellular system based on a scale-free user network and a power-law-distributed mobility model

Cellular design for a dense RFID reader environment

A reduced area 1 GSPS FFT design using MRMDF architecture for UWB communication

On output reorder buffer design of bit reversed pipelined continuous data FFT architecture

Fast locking and high accurate current matching phase-locked loop

A wide band and low PN PLL design for digital tuner

An electronically controllable dual-mode universal biquad filter using only single CCCCTA

High-order delta-sigma modulator with switched-current feedback memory cell

A novel two-channel time-interleaved forth-order sigma-delta modulator topology

A tunable SC bandpass delta-sigma modulator for multi-standard applications

A 1-V 90dB DR audio stereo DAC with embedding headphone driver

A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs

Current mode track and hold circuit with 50MS/sec speed and 8-bit resolution

A comparison of second-order sigma-delta modulator between switched-capacitor and switched-current techniques

A low-voltage high-gain wide-bandwidth class-AB differential difference amplifier

Wide-common-mode-range and high-CMRR CMOS OTA operable in both weak and strong inversion regions

Designing of a neuron MOS current mirror with a transimpedance amplifier

A CMOS low-voltage fully differential sample-and-hold circuit

A process- and temperature- insensitive current-controlled delay generator for sampled-data systems

An improved universal CMOS current-mode analog function synthesizer: Performance analysis

A precise bandgap reference with intrinsic compensation for current-mirror mismatch

A Sub-1ppm/°C high-order curvature-compensated bandgap reference

Feasible implementation of a prediction algorithm for the game of roulette

State-observer-based approach for identification and monitoring of complex dynamical networks

On the approximation errors in the frequency test included in the NIST SP800-22 statistical test suite

Powder RFID chip technology

A 0.8V SOP-based cascade multibit delta-sigma modulator for wideband applications

On the design of band-pass quadrature ΣΔ modulators

ΔΣAD modulator for low power application

An ultra low-power delta-sigma modulator using charge-transfer amplifier technique

A novel coefficient automatic calculation method for sinc filter in sigma-delta ADCs

Using asynchronous circuits for communications in wireless endoscopic capsule

Optical front-end receiver configuration for 30 GHz millimeter-wave signal Radio over Fiber system

A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications

Wideband double-UT RFID tag antenna design

A scalable distributed memory architecture for Network on Chip

Design and performance evaluation of a 2D-mesh Network on Chip prototype using FPGA

RaceCheck: A race logic audit program for ESL-based soc designs

The design and transport latency analysis of a locality-aware network on chip architecture

On-Chip-Network cryptosystem: A high throughput and high security architecture

Analysis-by-synthesis method for whisper-speech reconstruction

High pitch source isolation using complex cepstrum in the autocorrelation domain

Non-blind audio-watermarking using compression-expansion of signals

A frequency-based fast block type decision algorithm for intra prediction in H.264/AVC high profile

A low complexity modulo $2^{n}+1$ squarer design

A novel basic unit level rate control algorithm and architecture for H.264/AVC video encoders

Hardware development for pervasive healthcare systems: Current status and future directions

An efficient architecture for HWT using sparse matrix factorisation and DA principles

A new battery management system for li-ion battery packs

Design of off-chip capacitor-free CMOS low-dropout voltage regulator

A CMOS low-dropout regulator with 3.3 μA quiescent current independent of off-chip capacitor

Two-stage current-mode multiphase voltage doubler based on PWM control

Design strategy for 2-phase switched capacitor charge pump

Cost effective hardware sharing architecture for fast 1-D 8×8 forward and inverse integer transforms of H.264/AVC high profile

Architecture design of low-power and low-cost CAVLC decoder for H.264/AVC

Design of a memory-based VLC decoder for portable video applications

Transformed-based mode decision algorithm for H.264/AVC intraprediction

A block type decision algorithm for H.264/AVC intra prediction based on entropy feature

An integrated low power one-pin crystal oscillator

A 2.5Gb/s oversampling clock and data recovery circuit with frequency calibration technique

A DC-offset-compensated, CT/DT hybrid filter with process-insensitive cutoff and low in-band group-delay variation for WLAN receivers

A 90nm CMOS wide-band voltage-controlled ring oscillator for digital TV-tuner

A novel versatile circuit functioning as both filter and oscillator based on CCCCTAs

Design of passive UHF RFID tag in 130nm CMOS technology

Printed circuit antenna for UWB systems

Ku band voltage controlled oscillator on SiGe

A divide-by-3 frequency divider for I/Q generation in a multi-band frequency synthesizer

A 0.8V folded-cascode low noise amplifier for multi-band applications

A top-down, mixed-level design methodology for CT BP ΔΣ modulator using verilog-A

A Wideband three-stage rail-to-rail power amplifier driving large capacitive load

A novel schmitt trigger with low temperature coeficient

A full current-mode sense amplifier for low-power SRAM applications

A programmable duty cycle corrector based on delta-sigma modulated PWM mechanism

Sufficient conditions for non-negative impulse response of arbitrary-order systems

Generalized matrix method for efficient residue to decimal conversion

A low-cost continuous flow parallel memory-based FFT processor for Ultra-Wideband (UWB) applications

Efficient designs of flaoting-point CORDIC rotation and vectoring operations

Efficient structures for time delay estimation in time-varying environments

Efficient fast filter bank with a reduced delay

Precoded MIMO-SC-FDE and blind channel estimation

Subband adaptive filtering using approximately alias-free cosine modulated filterbanks

Delta operator based design of 1-D and 2-D filters: An overview

Intergrated control system of multi-channel audio signals for serial transmission

Design of high-performance transform and quantization circuit for unified video CODEC

Adaptive rate control for real-time video streaming over the mobile WiMAX

A compact DSP architecture for digital audio

Auto white balance system using adaptive color samples for mobile devices

Multi-direction search algorithm for block-based motion estimation

A low bandwidth integer motion estimation module for MPEG-2 to H.264 transcoding

Multi-direction search algorithm for block motion estimation in H.264 encoder

Two-step windowing technique for wide range motion estimation

Stereoscopic video generation from monoscopic compressed moving videos

A high-performance current-mode precision full-wave rectifier based on BiCMOS-CCCDBAs

Current controlled CCTA based- novel grounded capacitance multiplier with temperature compensation

A current-mode wheatstone bridge employing only single DO-CDTA

Low voltage, high performance first and third generation current conveyor in 0.18μm CMOS

Novel realization of voltage transfer function with fractional characteristics using CFAs

Scalable and parallel codec architectures for the DVB-S2 FEC system

An improved Montgomery inversion algorithm over $GF(2^{m})$ targeted for low area scalable inverter on FPGA

$GF(2^{m})$ multiplier using Polynomial Residue Number System

A new decoder for binary quadratic residue code with irreducible generator polynomial

An 8B/10B encoder with a modified coding table

A new BPSK demodulation circuit for command transmission in wireless implantable neural recording system

Voltage averaging technique for improving the resolution of two-capacitor DAC

Dynamic TDM virtual circuit implementation for NoC

The irradiation effect of DC-DC power converter under X-ray

A minimum-path mapping algorithm for 2D mesh Network on Chip architecture

New approaches to interconnect macromodeling with explicit delay extraction

A semi-monotonic routing method for fanin type Ball Grid Array packages

Arbitrary convex and concave rectilinear block packing based on O-Tree representation

Chip to chip communications for terabit transmission rates

High-speed mixed-signal SoC design for basestation application

High-speed serial interconnect transceiver: Applications and design

Accurate Bit-Error-Rate estimation for efficient high speed I/O testing

Multi-access memory architecture for image applications with multiple interested regions

Parallel implementation of morphological processing by arbitrary kernels on Cell/BE with OpenCV interface

A location map-free visible and reversible watermarking method with authentication ability

Reversibly sharing and hiding secret using expansion strategy

An architecture of photo core transform in HD photo coding system for embedded systems of various bandwidths

On the use of multi-tone for the measurement of noise power ratio distortion in RF circuits

Harmonic and IMD frequency components affecting nonlinear distortion with feed back in MOSFET amplifiers

An adaptive scheme for estimating and correcting RF amplifiers’ non-linearities

Linearization of table-based MOSFET Model parameters for nonlinear quantification

Behavioral modeling for operational amplifier in sigma-delta modulators with Verilog-A

Design of analog mixer for RF frontend

Signal estimation method for folding ADCs in wideband multistandard SWR receivers

Impact of circuit nonidealities on the implementation of switched-capacitor resonators

Electrical-level synthesis of pipeline ADCs

A ROM-less DDFS using a nonlinear DAC with an error compensation current array

Low-complexity shift-LDPC decoder for high-speed communication systems

Efficient decoder design for high-throughput LDPC decoding

An O(qlogq) log-domain decoder for non-binary LDPC over GF(q)

Efficient encoding for dual-diagonal structured LDPC codes based on parity bit prediction and correction

An IP generator for quasi-cyclic LDPC convolutional code decoders

Low power 32-bit UniRISC with Power Block Manager

Design of simple and high speed VLSI core for the protection of mass storages

Design and implementation of co-design toolset for tcore processor

Processor frequency assignment in three-dimensional MPSoCs under thermal constraints by polynomial programming

VLSI implementation and optimization design of Reed-Solomon decoder in QAM demodulation chip

Wire density driven top-down global placement for CMP variation control

Minimization of delay insertion in clock period improvement in general-synchronous framework

Timing-driven multi-layer Steiner tree construction with obstacle avoidance

Timing-constrained yield-driven redundant via insertion

Electromigration-aware rectilinear Steiner tree construction for analog circuits

Current-mode gigabit optical receivers in submicron CMOS technologies

A 4GHz direct digital frequency synthesizer utilizing a nonlinear sine-weighted DAC in 90nm CMOS

Current-sensing technique for current-mode DC-DC buck converter with offset-voltage compensation

A implementation of fully integrated frequency synthesizer For ISM band transceiver

A design of sub-band generator for MB-OFDM UWB application in 0.13 μm RF CMOS process

Characterization of structures maskless-etched by low-energy FIB

Asymmetric dual-gate multi-fin keeper bias options and optimization for low power and robust FinFET domino logic

An ultrahigh-speed full adder using resonant-tunneling logic gates

A novel optical mesh network-on-chip for gigascale systems-on-chip

A tight-binding model of the benzene-molecular system

A content-aware packets priority ordering and marking scheme for H.264 video over diffserv network

Adaptive partition size temporal error concealment for H.264

Pooled zero vector coding for enhanced compression of motion vectors

An adaptive interpolation scheme for inter-layer prediction

Efficient built-in self-test for video coding cores: A case study on motion estimation computing array

LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

SimSoC: A SystemC TLM integrated ISS for full system simulation

A proposed FPGA-based parallel architecture for matrix multiplication

BIST approach for testing configurable logic and memory resources in FPGAs

A fully-differential subthreshold SRAM cell with auto-compensation

A technique of automatic monitor generation based on FSM

Unknown response masking with minimized observable response loss and mask data

A chaos-based image encryption ASIC using reconfigurable logic

Compressor tree based processing element optimization in propagate partial SAD architecture

An asynchronous fixed-coefficient FIR filter implemented with flexible a-Si TFT technology

Fast sweeping methods for checking passivity of descriptor systems

A new modulo-N based digital clock synthesizer with an adjustable duty-cycle

Implementation of reconfigurable SHA-2 hardware core

High throughput 32-bit AES implementation in FPGA

A novel dynamic reconfigurable VLSI architecture for H.264 transforms

Efficient content based image retrieval through sector histogram

Construction of short-length LDPC codes with low error floor

3D map building based on projection of virtual height line

A survey on the structures of current mobile humanoid robots

A general model of a kind of parallel manipulator for active control based on KANE’s dynamics

Sliding mode control for trajectory tracking on mobile manipulators

Sufficient conditions and error analysis on radial equivalent circuit of multi-winding isolating transformers used in power electronic devices

A novel approach to eliminate zero-sequence harmonics current

Lessening zero sequence effects in dynamic voltage restorers

Controlled slew rate enhancement circuit for error amplifier in high frequency DC-DC converters

Clock control strategy of four-phase Dickson charge pump for power efficiency improvement

Analysis of coupled inductors for low-ripple fast-response buck converter

Integrated controller for a 100 MHz DC-DC switching converter

Comprehensive power analysis and efficiency optimum design for step-up DC-DC converters

Design method for monolithic DC-DC converters based on the losses optimization of the power stage

Design of a green mode PWM control IC

SDPQ classification based on maximum similarity principle of S-transform MTFM

Design of a 10 kVA HTS transformer prototype

HTS DC power transmission analysis

HTS inductive magnetic energy storage with power control technology

Decentralized coordinated robust adaptive control for AC/DC interconnected power systems based on WAMS

Visualization tool for transient stability monitoring of bulk power systems based on DSR

APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems

The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings.

Asia-Pacific Conference on Circuits and Systems

IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394)

IEEE. APCCAS 1998. 1998 IEEE Asia-Pacific Conference on Circuits and Systems. Microelectronics and Integrating Systems. Proceedings (Cat. No.98EX242)

Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems

A CMOS low-voltage fully differential sample-and-hold circuit

Content Provider	IEEE Xplore Digital Library
Author	Chi-Chang Lu Wei-Xiang Tung Chien-Kuo Huang
Copyright Year	2008
Description	Author affiliation: Dept. of Electr. Eng., Nat. Formosa Univ., Huwei (Chi-Chang Lu; Wei-Xiang Tung; Chien-Kuo Huang)
Abstract	A new technique for realizing a CMOS low-voltage fully differential sample-and-hold circuit is presented. A low-voltage technique is proposed for CMOS sample-and-hold circuit that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. For 2.5 MHz input signal frequency, the proposed sample-and-hold circuit exhibits a THD of -62 dB for 1.0 $V_{pp}$ input signal at 25 MHz sampling rate. Simulation results are given to demonstrate the potential advantage of the new technique.
Starting Page	1188
Ending Page	1191
File Size	434623
Page Count	4
File Format	PDF
ISBN	9781424423415
e-ISBN	9781424423422
DOI	10.1109/APCCAS.2008.4746238
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-30
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Voltage Switching circuits Clocks Sampling methods Timing Circuit simulation Operational amplifiers MOSFETs CMOS process
Content Type	Text
Learning Resource Type	Article

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