NDLI: A comparative study of single-phase clocked latches using estimation criteria

Content Provider	IEEE Xplore Digital Library
Author	Ghannoum, S. Chtchvyrkov, D. Savaria, Y.
Copyright Year	1994
Description	Author affiliation: Electr. Eng. Dept., Ecole Polytech., Montreal, Que., Canada (Ghannoum, S.; Chtchvyrkov, D.; Savaria, Y.)
Abstract	The advantage of using single-phase clocked circuits in VLSI system design is well known. This class of circuits has the advantage of simple clock distribution, low area for clock routing, reduced clock skew, and high speed. However, it is difficult to compare the characteristics and performance of these circuits, because there are no clear evaluation criteria. Indeed, such criteria are related to the application context and may therefore be misleading when taken out of context. In this paper, we will present a set of criteria which will permit designers to choose the most appropriate circuit in a particular case and therefore, obtain useful results. The proposed criteria will reduce the simulation time and help designers to reach better solutions in less design time.<>
Starting Page	347
Ending Page	350
File Size	397470
Page Count	4
File Format	PDF
ISBN	078031915X
DOI	10.1109/ISCAS.1994.409268
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-05-30
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Latches CMOS logic circuits Costs Very large scale integration Safety Timing Routing Circuit simulation Instruments
Content Type	Text
Resource Type	Article

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