NDLI: Design of FPGA-based Residue Number System Converters for Digital Signal Processing Systems

Content Provider	IEEE Xplore Digital Library
Author	Maslennikow, O. Maslennikowa, N. Rajewska, M. Gretkowski, D. Lienou, J.-P.
Copyright Year	2007
Description	Author affiliation: Dept. of Electron., Tech. Univ. of Koszalin, Koszalin (Maslennikow, O.; Maslennikowa, N.; Rajewska, M.; Gretkowski, D.)
Abstract	In this paper, two new and simple structures of the q-operands multi-operand modular adder have been proposed, which are adapted to realization in the Xilinx FPGA devices. The main purpose of new MOMA designs has been the reduction of hardware complexity of MOMAs by means reduction of a ROM volume. New adders are used in the residue number system converters based on the current-mode gates. This technology allows on further reduction of their hardware complexity in comparison with their prototypes based on the classical CMOS gates.
Starting Page	194
Ending Page	201
File Size	785582
Page Count	8
File Format	PDF
ISBN	9665335870
DOI	10.1109/CADSM.2007.4297523
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-02-19
Publisher Place	Ukraine
Access Restriction	Subscribed
Rights Holder	Lviv Polytechnic National University
Subject Keyword	Signal design Digital signal processing Hardware Read only memory Field programmable gate arrays Inverters Prototypes Adders Digital arithmetic Delay Current-mode gate Residue Number System Multi-Operand Modular Adder Binary to Residue and Residue to Binary Converters FPGA (Field Programmable Gate Array)
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design Of Fpga-based Multi-operand Modular Adders For Residue Number System Converters

Residue Arithmetic in FPGA Matrices

Study of multipliers in residue arithmetic using programmable logic

Full adder-based inner product step processors for residue and quadratic residue number systems

Iterative decimal multiplication using binary arithmetic

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set ${2n+1,2n,2n-1}$

Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder

VLSI Reverse Converter for RNS Based on the Moduli Set

Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications

Design of FPGA-based Residue Number System Converters for Digital Signal Processing Systems

Similar Documents

Design Of Fpga-based Multi-operand Modular Adders For Residue Number System Converters

Residue Arithmetic in FPGA Matrices

Study of multipliers in residue arithmetic using programmable logic

Full adder-based inner product step processors for residue and quadratic residue number systems

Iterative decimal multiplication using binary arithmetic

An Efficient FPGA Design of Residue-to-Binary Converter for the Moduli Set ${2n+1,2n,2n-1}$

Design of a Radix-2m Hybrid Array Multiplier Using Carry Save Adder

VLSI Reverse Converter for RNS Based on the Moduli Set

Evaluation of power efficient adder and multiplier circuits for FPGA based DSP applications

Design of FPGA-based Residue Number System Converters for Digital Signal Processing Systems