NDLI: Sub-micron BiCMOS process design for manufacturing

Please wait, while we are loading the content...

2015 IEEE Bipolar/BiCMOS Circuits and Technology Meeting - BCTM

2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

2013 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

2012 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

2011 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

2010 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM)

2009 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

2008 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting

2006 Bipolar/BiCMOS Circuits and Technology Meeting

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005.

Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting

2003 Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting (IEEE Cat. No.03CH37440)

Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting

Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212)

Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.00CH37124)

Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024)

Proceedings of the 1998 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.98CH36198)

Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting

Proceedings of the 1996 BIPOLAR/BiCMOS Circuits and Technology Meeting

Proceedings of Bipolar/Bicmos Circuits and Technology Meeting

Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting

1993 Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting

XFCB: a high speed complementary bipolar process on bonded SOI

UHF-1: a high speed complementary bipolar analog process on SOI

SOI: opportunities and challenges for sub-0.25 mu m VLSI

Signal conditioning circuitry for silicon pressure sensor

BiCMOS analog arbitration circuits

A quad low voltage rail-to-rail operational amplifier

A 500 MHz ATE pin driver

A high-voltage ATE pin driver

Characterization of low VAR bipolar transistors using a revised SPICE simulator

Simulation of bipolar VLSI circuits using overlapped relaxation technique

An analytical model for collector currents in gated lateral bipolar transistors

A semi-physical bipolar transistor model for the design of very-high-frequency analog ICs

Application of base drift field measurement to processing optimization of advanced bipolar transistors

An accurate quasi-static method for determining the excess phase shift in the base region of bipolar transistors

A method of measuring base and emitter resistances of AlGaAs/GaAs HBTs

A complete and consistent electrical/thermal HBT model

A Futurebus+ central arbiter based on pairwise mutual exclusion

A BiCMOS dynamic full adder circuit for VLSI implementation of high-speed parallel multipliers using Wallace tree reduction architecture

A new, 0.8 V logic swing, 1.6 V operational high speed BiCMOS circuit

3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs

A high-density 300 ps BiCMOS GRA

Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time

Power partition and emitter size optimisation for bipolar ECL circuit

A low-power static frequency divider circuit in bipolar technology

Static silicon frequency divider for low power consumption (4 mW, 10 GHz) and high-speed (160 mW, 19 GHz)

A 15.5 GHz bandwidth Si bipolar preamplifier

A 22 Gb/s decision circuit and a 32 Gb/s regenerating demultiplexer IC fabricated in silicon bipolar technology

Circuit design for a 15-Gb/s Si bipolar decision circuit

Design and evaluation of a 5 GHz HBT strobed comparator

A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages

Simulation of hot electron induced degradation in silicon bipolar transistors

Modeling the small-emitter effect in polysilicon-emitter transistors

New models for the simulation of polysilicon impurity diffusion sources for a wide range of process conditions

A novel VLSI process using electron irradiation and laser annealing

The effect of isolation edge profile on the leakage and breakdown characteristics of advanced bipolar transistors

Analysis of process margins for emitter-base self-alignment structures through a combination of simulation and experiment

Proton implantation in lateral IGBTs

Optimization of shallow and deep trench isolation structures for ultra-high-speed bipolar LSIs

A stacked emitter polysilicon (STEP) bipolar technology for 16 Mb BiCMOS SRAMs

An ultra-shallow link base for a double polysilicon bipolar transistor

A self-aligned emitter base NiSi electrode technology for advanced high-speed bipolar LSIs

Polysilicon-emitter bipolar transistors with interfacial nitride

Tailoring interfacial oxide for polysilicon bit-cell contacts and emitters with in situ vapor HF interface cleaning and polysilicon deposition in a 4 Mbit BiCMOS fast static RAM

Sub-micron BiCMOS process design for manufacturing

An 850 MHz current feedback operational amplifier

On-die parasitic effects and their impact on high-speed bipolar IC design

QPSK modulators for digital cellular communication

A bipolar IF device for GSM mobile telephone

Thermionic emission limited recombination in phosphorus-implanted polysilicon emitters

A comparative device and performance analysis between a Si-Ge epitaxial-base HBT and a Si double-poly I/I BJT npn structure

Extension of common-emitter breakdown voltage for high speed Si/Si/sub 1-x/Ge/sub x/ HBT's

Assumptions and trade-offs in device simulation programs

SHBT-a Schottky heterojunction bipolar transistor

SiGe drift base bipolar technology using Si-GeH/sub 4/ MBE for sub-40 GHz f/sub MAX/ operation

Microwave performance of InGaAs/InP composite collector bipolar transistors

Silicon epitaxial equipment and processing advances for bipolar base technology

Proceedings of the 1992 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.92CH3177-3)

Sub-micron BiCMOS process design for manufacturing

Content Provider	IEEE Xplore Digital Library
Author	Lau, C.K. Lin, C.-H. Packwood, D.L.
Copyright Year	1992
Description	Author affiliation: Hewlett-Packard Co., Palo Alto, CA, USA (Lau, C.K.; Lin, C.-H.; Packwood, D.L.)
Abstract	A 0.5- mu m BiCMOS process is used to illustrate the details in process design needed as a prerequisite for success in manufacturing. An existing CMOS process was used as the core for the BiCMOS process; CMOS design rules and performance were not altered by the addition of the bipolar processes. Issues related to bipolar integration, individual process modules, interactions between CMOS and bipolar, and manufacturability are discussed in detail. The specific performance targets for the bipolar devices are outlined. This process has been targeted to be used in building future high-performance ASIC products.<>
Starting Page	76
Ending Page	83
File Size	834875
Page Count	8
File Format	PDF
ISBN	0780307275
DOI	10.1109/BIPOL.1992.274079
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1992-10-07
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	BiCMOS integrated circuits Process design Manufacturing processes CMOS process CMOS logic circuits Costs Logic devices Application specific integrated circuits CMOS technology Logic arrays
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in