NDLI: Gate controlled vertical-lateral NPN bipolar transistor in 90nm RF CMOS process

Content Provider	IEEE Xplore Digital Library
Author	Zhiming Feng Shuo-Mao Chen Xie, C. Yan Cui Brunsman, M. Chao, C.P. Tseng, H.C. Guofu Niu Rezvani, G.A.
Copyright Year	2008
Description	Author affiliation: Semicond. Manuf. Co. (TSMC), Hsinchu (Chao, C.P.) \|\| RFMD Scotts Valley Design Center, Scotts Valley, CA (Zhiming Feng; Tseng, H.C.; Rezvani, G.A.) \|\| Inst. of Microelectron., Nat. Cheng Kung Univ., Tainan (Shuo-Mao Chen; Xie, C.; Yan Cui; Brunsman, M.)
Abstract	A new gate controlled bipolar transistor is introduced in this paper which combines the lateral and vertical bipolar effect in standard NMOS device in a 90 nm triple well process technology. A current gain of more than 200, cut off frequency of about 7 GHz, and lower flicker noise compared with CMOS devices were achieved without any change to process and/or introduction of any extra masking step. The impact of gate length, the role of vertical and lateral NPN components, and effect of emitter area on operation of this device are discussed.
Starting Page	29
Ending Page	32
File Size	254942
Page Count	4
File Format	PDF
ISBN	9781424427253
ISSN	10889299
DOI	10.1109/BIPOL.2008.4662706
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-10-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates MOS devices Noise Arrays Gain CMOS integrated circuits Current measurement
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	ndl-support@iitkgp.ac.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Libarray of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology

Design theory and fabrication process of 90nm unipolar-CMOS

Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technology

Vertical nanowire transistor-based CMOS: VTC analysis

SOI lateral bipolar transistor with drive current >3mA/μm

Lateral npn bipolar transistor for high current gain applications at reduced temperatures

A gate Modulated avalanche bipolar transistor in 130nm CMOS technology

Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

In/out pad electrostatic discharge protection for sub-micron integrated circuits based on lateral bipolar transistor

Gate controlled vertical-lateral NPN bipolar transistor in 90nm RF CMOS process

Similar Documents

A Low-Flicker Noise Gate-Controlled Lateral–Vertical Bipolar Junction Transistor Array With 55-nm CMOS Technology

Design theory and fabrication process of 90nm unipolar-CMOS

Sub-THz high gain wide-band low noise amplifiers in 90nm RF CMOS technology

Vertical nanowire transistor-based CMOS: VTC analysis

SOI lateral bipolar transistor with drive current >3mA/μm

Lateral npn bipolar transistor for high current gain applications at reduced temperatures

A gate Modulated avalanche bipolar transistor in 130nm CMOS technology

Close-in phase-noise enhanced voltage-controlled oscillator employing parasitic V-NPN transistor in CMOS process

In/out pad electrostatic discharge protection for sub-micron integrated circuits based on lateral bipolar transistor

Gate controlled vertical-lateral NPN bipolar transistor in 90nm RF CMOS process