NDLI: A novel high-performance low-power CMOS master-slave flip-flop

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15th Annual IEEE International ASIC/SOC Conference

Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558)

Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541)

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454)

Table of contents

Integrated Microsystems: Merging MEMS, micropower electronics, and wireless communications

Interconnect modeling and signal integrity issue I

Noise and delay uncertainty studies for coupled RC interconnects

Crosstalk delay analysis using relative window method

Optimizing RLC tree delays by employing repeater insertion

Performance enhancement through optimal n-tier multilevel interconnect architectures

SoC Verification

Verifying IP-core based system-on-chip designs

Formal verification: a new partial order approach

Target processor and co-verification environment independent adapter-a technology to shorten cycle-time for retargeting TI processor simulators in HW/SW co-verification environments

HDL simulation of microcontrollers

Interconnect modeling and signal integrity issues II

A negative feedback based substrate coupling noise reduction method

Design of dynamic circuits with enhanced noise tolerance

Settling time modeling of the ground bounce produced into the switching buffer

Efficient modeling techniques for IR drop analysis in ASIC designs

SoC design methodologies

SLDL: a systems level design language

Codesign paradigm in digital/analog tradeoffs

Methodology for ATM-cell processing system design

The VHDL-MOS package for transistor-level event-driven simulation

ASIC and SoC applications

A reconfigurable digital filter chip for image processing

The MDSP (Multimedia DSP) chip with an enhanced instruction set

An architecture for implementing VLC in VLSI technology based on microprogramming and hash tables

ASIC implementation using laser programmable multi chip modules (LPMCM)

Behavioral Synthesis

Effective design exploration through multi-objective high-level DSP synthesis

System exploration and synthesis from SDL of an ATM switch component

An integrated approach to data path synthesis for power optimization

Testability synthesis for jumping carry adder

Architecture of embedded zerotree wavelet based real-time video coder

ATLAS II: optimizing a 10 Gbps single-chip ATM switch

A single-chip solution for an ADM-1/TMX-1 SDH telecommunication node element

An ISM band RF front-end for short range wireless telemetry

G-vector: a new model for glitch analysis

Two-way circuit partitioning by iterative improvement and logic perturbation

CubicWare: a hierarchical design system for deep submicron ASIC

Utilization of carry-save-adders in arithmetic optimization

Procedures for the development of legacy processor systems and a procedure verifying case-study example

Efficient realization of FPGA-based two dimensional discrete cosine transform

An experimental hyper-bridge chip for a multimedia-data encoding system

A universal coprocessor and its application for an ADSL modem

Physical Design

Routability checking for general area routing problems

An evolutionary 3D over-the-cell router

A quadratic programming approach to clock skew scheduling for reduced sensitivity to process parameter variations

Efficient generation of timing and power polynomial models from lookup tables for SoC designs

Test strategies for SoC quality

AC/DC BIST for testing analog circuits

A universal march pattern generator for testing embedded memory cores

Event monitoring in a system-on-a-chip

Validation and test of systems on chip: a case study

Test ready core design for a DSP core

Global interconnect design for high speed ULSI and system-on-package

The impact of Cu/low /spl kappa/ on chip performance

ESD protection design and verification in a 0.35-/spl mu/m CMOS ASIC library

Impact of extrinsic and intrinsic parameter variations on CMOS system on a chip performance

Design of ultra low power pseudo-asynchronous SRAM

A new phase accumulator with single transistor path using pass transistor logic

Power analysis of gated pipeline registers

Low power parallel multiplier design for DSP applications through coefficient optimization

The active pixel CID-a new approach in electronic imaging

Switched-current technique for video compression and quantization

Second generation programmable artificial retina

A high-speed pixel-parallel fingerprint identifier for fingerprint identification system on a single chip

Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems

Asynchronous circuit completion detection by current sensing

Energy efficient filtering using adaptive precision and variable voltage

A solar powered letter scale with 45 /spl mu/W power dissipation

A new configurable and scalable architecture for rapid prototyping of asynchronous designs for signal processing

A novel high-performance low-power CMOS master-slave flip-flop

A 273 MHz low noise CMOS MR preamplifier for disk drives

ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

A wide-range low-jitter fully integrated programmable frequency synthesizer building block in a 2.5 V/0.25 /spl mu/m CMOS process

A frequency modulated PLL for EMI reduction in embedded application

A 200 MHz, 600 /spl mu/W CMOS PLL for mobile communication ASICs

A low-power video 10-bit CMOS D/A converter using modified look-ahead circuit

A low-power Viterbi decoder design for wireless communications applications

A modular and scalable architecture for the realization of high-speed programmable rank order filters

A fast VLSI implementation of sorting algorithm for standard median filters

A partial-polyphase VLSI architecture for very high speed CIC decimation filters

Intellectual property module of a highly parametrizable embedded stack processor

A parameterizable and process retargetable high speed DAC for digital radio applications

A reuse oriented design methodology for artificial neural networks implementation

High flexibility CMOS SRAM generator using multiplan architecture

Think hardware: behaviroal design reuse

Tutorial on interconnect modeling, signal integrity and reliability verification in deep sub-micron digital designs

Low power design for systems on a chip

Hardware/software co-design

High-performance interconnect design for systems-on-chip

Noise immune ASIC design

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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