NDLI: Implementation of high performance buffer manager for an advanced input-queued switch fabric

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Proceedings. IEEE Asia-Pacific Conference on ASIC,

2002 IEEE Asia-Pacific Conference on ASIC. Proceedings (Cat. No.02EX547)

A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture

Transfer function design of stable high-order sigma-delta modulators with root locus inside unit circle

A low-distortion and swing-suppression sigma-delta modulator with extended dynamic range

A CMOS current-mode band-pass filter with small chip area

Analog circuit for sound localization applications

A new low-voltage CMOS 1-bit full adder for high performance applications

Fast and compact dynamic ripple carry adder design

A novel self-repairable parallel multiplier architecture, design and test

A new pipelined divider with a small lookup table

Implementation of high performance buffer manager for an advanced input-queued switch fabric

Structure configuration of low power register file using energy model

A selectively accessing TLB for high performance and lower power consumption

A 4-KB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

A new 4-phase charge pump without body effects for low supply voltages

Self-isolated gain-enhanced sense amplifier

A 39-46 GHz MMIC HBT triple-push VCO using cascode configuration

A 2.5 Gbps CMOS laser diode driver with preemphasis technique

A 5.5 GHz prescaler in 0.18 /spl mu/m CMOS technology

A 2.5 Gbps CMOS data serializer

2.5 Gbps CMOS laser diode driver with APC and digitally controlled current modulation

A novel systolic VLSI architecture for fast RSA modular multiplication

A high-throughput low-cost AES cipher chip

A Rijndael cryptoprocessor using shared on-the-fly key scheduler

An efficient implementation of hash function processor for IPSEC

A staged carry-save-adder array for Montgomery modular multiplication

Tunable injection current compensation architecture for high fill-factor self-buffered active pixel sensor

A novel logarithmic response CMOS image sensor with high output voltage swing and in-pixel fixed pattern noise reduction

A cross-check test scheme for infrared focal plane array

High Q broadband copper spiral inductors with Q=45 on proton-bombarded semi-insulating silicon substrate

A 2.4 GHz Bluetooth transceiver in 0.18 /spl mu/m CMOS

A programmable filter with self-tuning for DMT VDSL receiver

A dual-loop automatic gain control for infrared communication system

A low power CMOS adaptive line equalizer for fast Ethernet

A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation

Explicit transfer function of RC polyphase filter for wireless transceiver analog front-end

Spread-spectrum clocking in switching regulators to reduce EMI

Design of negative charge pump circuit with polysilicon diodes in a 0.25 /spl mu/m CMOS process

System-level requirements of DC-DC converters for dynamic power supplies of power amplifiers

A comprehensive power analysis and a highly efficient, mode-hopping DC-DC converter

High-speed class AB buffer amplifiers with accurate quiescent current control

A high performance class AB CMOS rail to rail voltage follower

A track-and-hold circuit using a tail current source dividing technique

A 33 mW 12-bit 100 MHz sample-and-hold amplifier

A 3.3 V-110 MHz 10-bit CMOS current-mode DAC

A two-step A/D converter in digital CMOS processes

A 1 V CMOS analog comparator using auto-zero and complementary differential-input technique

High performance 1 V 2.4 GHz CMOS VCO

Phase noise analysis of an integrated voltage-controlled oscillator with a novel graphical optimization method

Two MOSFET-C low-voltage fully differential voltage-controlled oscillators for frequency tuning

The CMOS on-chip oscillator based on level tracking technique

Voltage controlled ring oscillator with wide tuning range and fast voltage swing

A 64 bit parallel CMOS adder for high performance processors

Reusable embedded debugger for 32 bit RISC processor using the JTAG boundary scan architecture

An 8-way VLIW embedded multimedia processor with advanced cache mechanism

Low cost floating point arithmetic unit design

A new floating-point normalization scheme by bit parallel operation of leading one position value

Power efficient MPEG-4 decoder architecture featuring low-complexity error resilience

ASIC implementation of a new and efficient wavelet coding algorithm

Single chip video segmentation system with a programmable PE array

Real-time segmentation architecture of gray-scale/color motion pictures and digital test-chip implementation

A novel motion estimation algorithm and its VLSI architecture

Analysis and design of CMOS broadband amplifier with dual feedback loops

Low noise amplifier circuit for bandpass sampling

The noise and linearity optimization for a 1.9-GHz CMOS low noise amplifier

Analysis of on-chip spiral inductors using the distributed capacitance model

A low power, wide operating frequency and high noise immunity half-digital phased-locked loop

A V-driver circuit for lowering power of sub-0.1/spl mu/m bus

0.9-V sense-amplifier-based reduced-clock-swing MTCMOS flip-flops

An all-digital PLL clock multiplier

Delay-difference DLL and its-application on skewed output buffer

High-speed low-complexity implementation for data weighted averaging algorithm [/spl Sigma//spl Delta/ modulator applications]

A sub-word parallel digital signal processor for wireless communication systems

A novel block equalization design for wireless communication with ISI and Rayleigh fading channels

Design and implementation of a scalable fast Fourier transform core

Design and implementation of an acoustic echo canceller

A real-time lipreading LSI for word recognition

A 0.18-/spl mu/m CMOS offset-PLL upconversion modulation loop IC for DCS-1800 transmitter

A direct-conversion CMOS receiver for 5 GHz wireless LAN

A 0.35-/spl mu/m SiGe BiCMOS RF front-end IC for TD-SCDMA receiver

A quadrature modulator with enhanced harmonic rejection filter

Wideband impedance matched GaInP/GaAs HBT Gilbert micromixer with 12 dB gain

Automatic Verilog code generation of an 8-bit RISC micro-controller

A high performance function generator for multiplier-based arithmetic operations

Memory synthesis for low power ASIC design

An exact algorithm for practical routing problems

A programmable data background generator for march based memory testing

A low-power Reed-Solomon decoder for STM-16 optical communications

A comma-free Reed-Solomon decoder chip for W-CDMA/FDD applications

VLSI design of a reconfigurable multi-mode Reed-Solomon codec for high-speed communication systems

A VLSI architecture of DMT based transceiver for VDSL system

Design of a DMT-based baseband transceiver for very-high-speed digital subscriber lines

All digital CDMA upstream transmitter and baseband VLSI design of head-end receiver for upstream cable networks

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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