NDLI: A dynamic logic circuit embedded flip-flop for ASIC design

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Proceedings. IEEE Asia-Pacific Conference on ASIC,

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

A 200 MHz/90 dB gain range CMOS VGA

A 0.35-/spl mu/m CMOS low noise VGA

Design of log domain low-pass filters by MOSFET square law

A low-ripple switched-capacitor DC-DC up converter for low-voltage applications

New plus- and minus-voltage generators for TFT-LCD panels

A dynamic logic circuit embedded flip-flop for ASIC design

New 4-transistor XOR and XNOR designs

CSPL: a capacitor-separated pass-transistor logic

CMOS capacitor coupling logic (C/sup 3/L) circuits

The non-full voltage swing TSPC (NSTSPC) logic design

Bi-directional current-mode multiple input maximum circuit

Design of 3.3 V 10 bit current-mode folding/interpolating CMOS A/D converter with an arithmetic functionality

Design of a geometric-mean generator based on switched-current technique

8-mW, 1-V, 100-Msps, 6-bit A/D converter using a transconductance latched comparator

A 10-bit, 40 Msamples/s cascading folding and interpolating A/D converter with wide range error correction

A differential type CMOS phase frequency detector

Adaptive AC/DC output buffer with reduced ground bounce and output ringing

Novel output buffer design for Universal Serial Bus applications

A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm

A self-timed wave pipelined adder using data align method

A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching

A CMOS voltage-controlled oscillator with temperature compensation

Design of high speed CMOS prescaler

A 2 V clock synchronizer using digital delay-locked loop

A 16.3-GHz 64:1 CMOS frequency divider

A low-power 1.2 GHz 0.35 /spl mu/m CMOS PLL

A low-complexity frame memory compression algorithm and its implementation for MPEG-2 video decoder

A programmable sensor signal conditioning LSI

A novel rotational VLSI architecture based on extended elementary angle set CORDIC algorithm

A 1-V low power rail-to-rail analog CMOS multi-function filter with configurable capability

A novel FPGA design of a wireless block transmission channel equalizer

A new VLSI design for adaptive frequency-detection based on the active oscillator

A hybrid-level multi-phase charge-recycler with reduced number of external capacitors for low-power LCD column drivers

A design of contrast controller for image improvement of multi-gray scale image

A smart image sensor with novel implementation of quad-tree scan

Optimized VLSI design for enhanced image downscaler

VLSI processor of parallel genetic algorithm

Analysis and implementation of interface for heterogeneous system

Static-based verification of memory BIST integration

A 2-V CMOS 455 kHz FM/FSK demodulator using feedforward offset cancellation limiting amplifier

3R one chip CMOS IC at 156 Mbit/s

A /spl Sigma/-/spl Delta/ modulator architecture reducing intermodulation of tones near f/sub s//2 into the baseband

High-frequency intermodulation analysis of cascode amplifier

Integrated mixer design

Efficient 8-cycle DES implementation

VLSI implementation of an OFB processor for encryption of real-time data

Hardware implementation of 128-bit symmetric cipher SEED

Asynchronous implementation of 1024-bit modular processor for RSA cryptosystem

Asynchronous implementation of modular exponentiation for RSA cryptography

Design of an equalizer using the DFE structure and the MMA algorithm

A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector

A 3 V 10 b 100 MS/s digital-to-analog converter for cable modem applications

A QPSK/16 QAM receiver chip for LMDS application

A new CMOS double-upconverter with half-LO for DTV tuner

An interpolation algorithm by using the adaptive pseudomedian filter

The design of the perspective texture mapping for 3D computer graphics in rasterizer merged frame buffer technology

Efficient simultaneous rounding method removing sticky-bit from critical path for floating point addition

Interface synthesis for IP based design

An efficient system to develop various soft IPs

A dual-band receiver architecture for PCS and IMT-2000

A 2 GHz LC-oscillator with automatic swing control for IMT-2000 application

Cost-effective low-power architecture of vestigial sideband W-CDMA system

1:N interpolation FIR filter design for SSB/BPSK-DS/CDMA

A novel architecture of rake receiver for fast acquisition

AE32000: an embedded microprocessor core

Enhancement of wafer test/package yields by oxide-capping of microlens in CMOS image sensor

Proven single pass design methodology for high reliable VDSM

Linear search algorithm for repair analysis with 4 spare row/4 spare column

An efficient implementation of BIST for floating point DSP processor

Test methodology for low power SRAM's (Is Iddq test useful for low power SRAM's?)

Testability features of the MDSP [Multimedia Fixed Point Digital Signal Processor]

CalmRISC/sup TM/-32: a 32-bit low-power MCU core

Efficient random vector verification method for an embedded 32-bit RISC core

Testability strategy and DFT methodology of CalmRISC32

A dynamic TLB management structure to support different page sizes

iSAVE: a behavioral emulator for in-system algorithm verification

Transition count based BIST for detecting multiple stuck-open faults in CMOS circuits

Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip

Designing built-in self-test circuits for embedded memories test

Design-for-testability of the FLOVA

The cache memory system for CalmRISC32

The design and implementation of CalmlRISC32 floating point unit

A hardware reduced multiplier for low power design

An embedded 16-bit microprocessor

A cost-effective 16-bit embedded flash MCU for digital multimedia applications

A novel analog mirror type DLL suitable for low voltage operation with self-calibration method

Interconnect strategy in deep-submicron DRAM technology

A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC)

Long retention time of embedded DRAM macro with thin gate oxide film transistors

Low voltage protection circuit for FeRAM macro

A regularly structured parallel multiplier with non-binary-logic counter circuits

A 4-way VLIW embedded processor and its companion chip

3D graphics system with VLIW processor for geometry acceleration

Building a crosstalk library for relative window methods-timing analysis that includes crosstalk delay degradation

Design of a noise-free microcontroller

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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