NDLI: A new lower power Viterbi decoder architecture with glitch reduction

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Proceedings. IEEE Asia-Pacific Conference on ASIC,

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

A 120 MHz SC 4th-order elliptic interpolation filter with accurate gain and offset compensation for direct digital frequency synthesizer

Design and analysis of symmetric dual-layer spiral inductors for RF integrated circuits

Synthesis and design of a 6th order SC lowpass decimator combining externally and internally cascaded structures

A filter for low EMI and low noise

Design and implementation for 125 mW/MIPS ultra-high speed low power asymmetric digital subscriber line transceiver chip

Design and simulation of three ATM ASICs

Design of 250 Mb/s 10-channel CMOS optical receiver array for computer communication

The low-area of new arc-tangent look-up table and a low overhead for CATV modem systems

Architectural design and implementation of full ATM layer functions for the cost effective access network

A digital signal processor for low power

A fail-safe microprocessor using dual synthesizable processor cores

A scheduling algorithm for pipelined data path synthesis with gradual mobility reduction

Realization of current-mode multifunction filters using multiple-output current conveyors

Design techniques for low-voltage VHF BiCMOS G/sub m/-C filters with automatic tuning

A 1.8 V self-biased complementary folded cascode amplifier

A new base driving technique of a high voltage BJT for the horizontal deflection output using a CRT

A frame-based symbol timing recovery for large pull-in range and small steady state variation

A class AB BiCMOS PCS driver amplifier with external gain control

A new lower power Viterbi decoder architecture with glitch reduction

A very low-noise high-transimpedance preamplifier IC for regenerated optical data transmission systems

A GHz I-Q quadrature signal generator using cellular oscillator network

A semi-folded instruction format for VLIW architecture

An inner product processor design using novel parallel counter circuits

Cost/performance trade-off in floating-point unit design for 3D geometry processor

Implementation of a cycle-based simulator for the design of a processor core

A CMOS analog vector quantizer for pattern recognition

A temperature sensor in 0.6 /spl mu/m CMOS technology

A universal sensor signal conditioning ASIC

An ASM-based ASIC for automobile accelerometer applications

High power 30 W and high efficiency 80% piezoelectric transformer for EB

A high-performance low-power asynchronous matrix-vector multiplier for discrete cosine transform

A VLSI implementation of MPEG-2 AAC decoder system

IP design of a reconfigurable baseline JPEG coding

A multimedia DSP chip for portable applications

66 M/70 mW HS and ultra-low power 16/spl times/16 MAC design using TG for web-based multimedia system

A 50% power reduction scheme for CMOS relaxation oscillator

Multi-level approaches to low power 16-bit ALU design

VLSI architecture for low power motion estimation using high data access reuse

High efficient 3-input XOR for low-voltage low-power high-speed applications

A 1.5 V 10-bit 25 MSPS pipelined A/D converter

A 12 bit current-mode folding/interpolation CMOS A/D converter with 2 step architecture

Design of an 8-bit 100 KSPS 1 mW CMOS A/D converter for digital mobile communication

A 3 V 10 b 70 MHz digital-to-analog converter for video applications

A calibration-free 3.0 V 12-bit 20 MSPS A/D converter

A low-power matrix transposer using MSB-controlled inversion coding

A lossless index coding algorithm and VLSI design for vector quantization

A novel FPGA design of a high throughput rate adaptive prediction error filter

A scalable high-precision CMOS max/min circuit using single comparator

Low-power full-search motion estimator architecture suitable for random-block match

A dual issue queued pipelined Java processor TRAJA-toward an open source processor project

RAPTOR: a single chip multiprocessor

Scalable latency tolerant architecture (SCALT) and its evaluation

A simulation efficiency improvement method for simulation-based analog cell synthesis

IP development and management of IP DB enabling efficient system-on-chip design

Simple analog nonlinear circuits for neural networks

Design of a 3/sup rd/ order CMOS sigma-delta modulator with faster conversion rates using zero-pole canceling technique

Overloading in multistage sigma-delta modulators

A VLSI design of hierarchical search motion estimation processor chip

An image processor for SXGA/UXGA FPD

Extrapolation for band-pass characteristics by using genetic algorithm on the DCT

Implementation of 13 kbps QCELP vocoder ASIC

Sequential design of a 8192 complex point FFT in OFDM receiver

IEEE 1284 softcore-implementation issues

Reduced IEEE 1284 soft IP design for system IC implementation

Reusable design of run length coder for image compression application

Reusable intellectual property cores in PC data protection ASIC design

A process and temperature compensated ring oscillator

A 3.3 V high speed CMOS PLL with a two-stage self-feedback ring oscillator

A 0.7-1 Gb/s CMOS clock recovery circuit

An on-chip automatic tuning circuit with VCO for multi-bit A/D-D/A calibration

A 1 V built-in intermediate voltage sensor

Boundary scan design and verification flow using buffer chain method

Design with testability for a platform-based SoC design methodology

Exceeding test pattern limitation by multi-clock test methodology

Input grouping method considering nodal connectivity for BIST test time reduction

A 32/spl times/32 self-timed multiplier with early completion

QAM/VSB dual mode equalizer design and implementation

Reconfigurable shared buffer ATM switch

Pattern generation for verification of VHDL behavioral-level design

High speed analog memory integrated circuit for Cherenkov telescopes

Wide operating-range acquisition technique for PLL circuits

Analog integrated circuit design for the wireless bio-signal transmission system

A delay locked loop circuit with mixed-mode tuning

Logic cell design for on-line testable FPGAs

New scan design of asynchronous sequential circuits

On using ATPG vectors for BIST TPG

Test ready core design for TeakLite core

Digitally programmable DC-DC voltage down converter

Adaptive hardware evolution under unpredictable environmental changes

A 30-V row/column driver for PSCT LCD using high-voltage BiMOS process

A 100 V, 10 mA high-voltage driver ICs for field emission display applications

A memory access system for merged memory with logic LSIs

A VPM (Virtual Pipelined Memory) architecture for a fast row-cycle DRAM

An effective routing methodology in the era of 0.2 /spl mu/m and beyond technologies for reducing the DRAM design cost

A 3-cycle lock time delay-locked loop with a parallel phase detector for low power mobile systems

A nightmare for CDMA RF receiver: the cross modulation

A 2 V CMOS programmable pipelined digital differential matched filter for DS-CDMA system

Optimum windows of DRAM input impedance (Lin,Cin,Rin) on data bus for 800 MHz signaling

RF characterization of deep-submicron DRAM-embedded CMOS process

A high performance DSP architecture "MSPM" for digital image processing using embedded DRAM ASIC technologies

A 48-pin "minichip" implementation of baseband analog processor for the CDMA mobile phones

A novel architecture design for multicode CDMA rake receiver

Realization of high-Q inductors using wirebonding technology

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