NDLI: An eight-channel analog signal processor for VoP applications

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ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549)

Performance-driven placement of multi-million-gate circuits

System-on-Chip design

System modeling with SystemC

Design verification using formal techniques

Verifying sequential behavior with model checking

A semi-formal verification methodology

Research on floorplanning

Technology roadmap on SOC testing: issues on SOC testing in DSM era

Techniques to remove false paths in statistical static timing analysis

Challenges on global routing correlation

The selection and creation of the rules in rules-based optical proximity correction

Studies on the layout algorithm for CGH in OEMCM systems design

Modeling switched-current functional block circuits using VHDL-AMS language

Design issues of deep submicron wave pipelining technology

A timing model of GHz e-shape interconnection

A performance analysis method of asynchronous data-path

Sub-graph matching based HW/SW co-design

A frequency domain fast wavelet collocation method for high-speed circuit simulation

Using a hardware model checker to verify software

A new modeling technique based on the ANN and DOE for interconnects

Computer aided design of switched-current filters

Greedy algorithm for register-transfer level ALU mapping

A modified data cache management scheme based on NTS structure

VLSI placement with pre-placed modules based on less flexibility first principles

Methods of improving rout ability in timing-driven placement

An efficient congestion optimization algorithm for global routing based on search space traversing technology

CEP: a clock-driven ECO placement algorithm for standard-cell layout

A mixed mode placement algorithm for combined design of macro blocks and standard cells

A new channel routing algorithm based on Steiner minimum tree

ASICosyn: co-synthesis of conditional task graphs with custom ASICs

Improving circuit simulation accuracy by partitioning algorithm

Distinguishing variables of Boolean function via distinct subBDDs

A compact algorithm for placement design using corner block list representation

Boolean matching algorithm based on the perfect matching of the bipartite graph

Behavioral modeling of electronic circuit module with Verilog-A language

Folding pipeline architecture based on the least-energy algorithm for high level synthesis

Library building technique for high-reliability submicron ASIC

VLSI/PCB placement with predefined coordinate alignment constraint based on sequence pair

CFG in sub-graph matching based HW/SW Co-Design

An improved chip level thermal analysis algorithm using BEM

Effects of delay models on maximum power estimation of VLSI circuits

A clustering-based algorithm for zero-skew clock routing with buffer insertion

A proof of boundary integral equations of minimum order for the calculation of 3-D eddy current problem

EVBCS: new equivalence verification algorithm based on OBDD and circuit structure

Integrated floorplanning and power supply planning

Edge based layout compaction

High-level library mapping based on polynomial representation

An object-based approach to optical proximity correction

Embedded nonvolatile memories

Low power design of embedded NOR type FLASH memory module (EFMM)

Performance analysis of sampling switch structures for wideband sigma-delta noise shapers for RF applications

A temperature-insensitive VCO and derivative PWM signal generator

A low-voltage high-speed sampling technique

Design of linear transimpedance amplifiers

Enhancement of attenuation poles at finite frequencies in six-pole microstrip quasi-elliptic filter

An eight-channel analog signal processor for VoP applications

A new on-chip DC-DC voltage down converter for low-power VLSI chip

A high bandwidth g/sub m/-constant rail-to-rail CMOS op amp for low voltage VLSI systems

Using pulsed activation to design a wide dynamic range PWM neuron circuit

A design of CMOS voltage doubler for 1 V operation

A novel low jitter PLL clock generator with supply noise insensitive design

Implementation of an analog self-learning neural network

A two-phase, four and five boosting ratio, charge pump cell for LCD driver

A CMOS bandgap reference circuit

A new structure, 200-MHz, -60 dB distortion linedriver for 1000Base-T Ethernet

The RF interface circuits design of contactless IC cards

Design of fully differential fourth-order Bessel filter with accurate group delay

Low voltage single-stage amplifier with wide output range

A MOCCII current-mode KHN filter and its non-ideal characteristic research

An 8-bit 125 MHz folding and interpolating analog-to-digital converter

Error-suppressing encoding structure of competition in flash A/D converter

Design of hybrid SET-CMOS D/A converter

Precise modeling of A/D converter and the macromodel of AD1380

Study and design of a 16-bit oversampling /spl Sigma/-/spl Delta/ A/D converter

Design of a 11 bit 10Ms/s pipelined A/D converter

Low voltage self-biasing reference circuits

Universal current-mode filter with three inputs using CCII+/

An improved push-pull Class-E RF tuned power amplifier with low maximum transistor current

Supply-adaptive rail-to-rail CMOS OPAMP

Clock and data recovery circuit for 2.5Gbps Gigabit Ethernet transceiver

Distributed cache-sorting-based label search engine for MPLS over ATM

Compression ratio and decompression overhead tradeoffs in code compression for VLIW architectures

An efficient and scalable VLSI implementation of DES

The design and implementation of a block cipher ASIC

A new RSA cryptosystem hardware implementation based on high-radix Montgomery's algorithm

A 1024-bit RSA crypto-coprocessor for smart cards

An embedded RSA processor for encryption and decryption

Fast modular multiplication with carry save adder

System-on-a-chip architecture for W-CDMA baseband modem LSI

Tradeoffs in modified discrete cosine transform implementations

An SC CCIR-601 video restitution filter with 13.5 Msample/s input and 108 Msample/s output

A high-throughput systolic array for motion estimation using adaptive bit resolution

Design and implementation of HDTV PES encoder

Automatic fingerprint identification system for small sized database

Implementation of MPEG-2 transport stream remultiplexer with CPLD

An efficient VLSI architecture for 2D-DCT using direct method

A high-speed, programmable, CSD coefficient FIR filter

ASIC design of Gabor transform for speech processing

Low entropy block matching algorithm for motion estimation

An architecture and implementation of image scaling conversion

FPGA implementation of IS-95 CDMA baseband filter

Design of constant-coefficient multipliers

64QAM trellis-decoding with channel state information

The correction of frequency-dependent I/Q mismatches in quadrature receivers by adaptive signal separation

An x/sin (x) FIR digital filter for DVB-C/DAVIC modulator

Estimation of E/sub b//N/sub 0/ at base-band processing for satellite communication

A VLSI implementation of a low complexity Reed-Solomon encoder and decoder for CDPD

VLSI design and architecture of a VC-Merge capable crossbar switch on MPLS over ATM

Design and implementation of concatenated encoder

A new VLSI design for decoding of Reed-Solomon codes based on ASIP [HDTV]

Design of a high performance Reed-Solomon decoder with switch box control logic [HDTV]

Decrease power consumption using a programmable logic device

Efficient design of application specific DSP cores using FPGAs

A novel FPGA implementation of SDH Equipment Clock

Real-time duplex digital video surveillance system and its implementation with FPGA

The implementation of digital protection in power system using FPGA

A novel configurable analog unit architecture

Experimental verification of the principle of operation of building blocks of 0.6 volt Si and SiGe vertical dual carrier field effect transistor FPGA with effective channel length of 5-20 nm

A study on implementing wavelet transform and FFT with FPGA

Application of platform FPGAs in W-CDMA

Logic design on FPGA of ATM SAR function in broadband access network

Design of VXIbus register based interface based on VHDL

Circuit design and implementation for digital temperature and humidity measurement and control

An approach to the single-chip arbitrary waveform generator (AWG)

MPEG-2 TS generate system and its implementation with FPGA

FPGA hardware devices with single-instruction driving for an embedded mobile computing platform

A FPGA-based implementation of data acquisition and processing for digital protective relays

Implementation of MPEG-2 transmission multiplexer with FPGA

The design of general-purpose parallel interface based on CPLD

Architectural adaptation for power and performance

ASIC design in HDTV modulation and demodulation application

Efficient correlator implementation in programmable logic

Non-binary (7, 2)-(9, 2) parallel counters for multiplier designs

A fine-grain asynchronous pipeline reaching the synchronous speed

Design of a low latency high speed pipelining multiplier

Multi-clock driven system: a novel VLSI architecture

Design techniques of CMOS SCL circuits for Gb/s applications

A new type of bootstrapped charge-recovery logic circuit

A fast low power embedded cache memory design

VHDL modeling and analysis of error-control specific circuits for multiple-modular redundant systems with concurrent error location capability

High-speed parallel multiplier with redundant-code algorithm using multiple-valued MOS current-mode circuits

Designing AHB/PCI bridge

A high speed 0.25 /spl mu/m 64-bit CMOS adder design

A flash IC card with programmable security code

Speed and resource issues on algorithm design and implementation with hardware

Ultra-high speed parallel multiplier with new first partial product addition algorithm

A high performance MAC design using proposed low power IP-cells

Low power design in 100 MHz embedded SRAM

The application of redundant encoding in iterative implementation of division and square root

How to generate tests using semi-formal technique: industrial experiences

Study of test approach for IP cores applicable to SOC designs

Design of mixed-signal circuit for testability

An approach to reducing power consumption during delay test application

Scan test in 18/spl times/18 bits Booth coding-Wallace tree multiplier

Study on UIO sequence generation for sequential machine's functional test

A new self-test structure for at-speed test of crosstalk in SoC busses

The design of a novel low-power and high-precision voltage testing circuit

Programmable Josephson AC-voltages will work well for analog DFT for mixed-signal ICs under background noise even up to 20 nanovolts

A new low power BIST methodology by altering the structure of linear feedback shift registers

A multilevel test approach and its application in microcomputer fault diagnosis

A new software for test logic optimization in DFT

An novel solution for testing power and testing time

Simulation of RF circuits with a PDE model of the MOSFET

Global modeling and simulation of System-on-Chip embedding MEMS devices

An analytical linearization method for CMOS MMIC power amplifier using Multiple Gated Transistors

MOSFET parameters extraction in VDSM ULSI CAD with a parallel-programming strategy

Organizing and storing of discretized BEM equations in 3D multi-dielectric parasitic capacitance extraction

Parameter extraction of threshold voltage model of BSIM3V3

QFP package analysis using partial element equivalent circuits

A hierarchical circuit extraction based on scan line

Module recognition and its application to LVS of ASIC

A new usage of SPICE simulation program [bipolar transistor]

Parallel behavior-level simulator based on VHDL-AMS [mixed circuit simulation]

Mixed-signal behavioral modeling for QPSK digital communication system

Parameter extraction of BSIM based on S/sup 3/ theory

Hierarchical h-adaptive computation in VLSI interconnect capacitance extraction

Coupling computation of the BEM and FDM in 3D capacitance extraction

Conductor cross-section moment method applied in integrated circuit interconnects resistance and inductance parameter extraction

A novel technique for behavioral modeling of the second generation switched-current building block circuits

A design methodology of vector unit for Emotion synthesis

A Java processor suitable for applications of smart card

Testing IP cores with pseudo exhaustive test sets

Parameterized IP core design

A high speed microprocessor core for the embedded applications-PKURS001

Implementation of an 8-bit embedded microprocessor for smart cards

IP reusable design methodology

The design of a 32 bit floating-point RISC microprocessor

The design of a high performance and low power embedded microprocessor core OM80C51

Formal verification of embedded SoC

A scalable test mechanism and its optimization for test access to embedded cores

A debug sub-system for embedded-system co-verification

A platform for system-on-a-chip design prototyping

Optimizing the design for microdisplay on silicon, creating IP modules for a new type of SOC

A modified microprogramming control for FPU

MT ARM: multithreading implementation in Arm7 architecture

Design and VLSI implementation of an asynchronous low power microcontroller

Challenges in RF analog integrated circuits

Design of highly integrated RF chip-sets for GSM cellular handsets

A 1 GHz analog multiplier with shunt-peaked LNA core

A 0.18-/spl mu/m CMOS LNAs with sub-2 dB NF and low power for Bluetooth applications

A 3.3-V, 2-GHz CMOS low noise amplifier

2.5-Gb/s 0.35-/spl mu/m CMOS laser-diode driver

A novel CMOS quadrature VCO based on symmetrical spiral inductors and differential diodes

The performances comparison between DLL and PLL based RF CMOS oscillators

Design of the CMOS low noise amplifier in the GPS receiver

A novel digital demodulation method for CPFSK and its realization

A high-performance RF bandpass prefilter

Wireless systems-on-chip

Memory and logic integration for System-in-a-Package

Solid-state sensors for microsystem applications

An improved low power CMOS readout circuit for focal plane array

High efficient energy recovery logic for adiabatic computing

A truly random number generator based on thermal noise

Optimized design of OPA in focal plane array readout circuits

An instruction fetch unit applicable to 32-bit and 16-bit instruction sets together

Car collision-prevention radar system

Switching and analog performance of 0.6 volt, 20 nm effective channel length Si ASIC Dual Carrier Field Effect Transistor and three dimensional field effect transistor

Study on self-heat effects in integrated circuits with hot-spot and electro-thermal coupling methods

Adiabatic NP-domino circuits

2nd International Conference on ASIC

An eight-channel analog signal processor for VoP applications

Content Provider	IEEE Xplore Digital Library
Author	Liang Zhang Gang Yan Xin Liu Jian Wang Shubing Zhai Gang Shan Song Gao Haichuan Liu Zhongyuan Chang Yang, H.C.
Copyright Year	2001
Description	Author affiliation: IDT-Newave Technol. Co. Ltd., Shanghai, China (Liang Zhang)
Abstract	In this paper we present the first single-chip 8-channel voice codec with enhanced features for voice over packet (VoP) and high density line card applications. Sigma-delta modulators are used for A/D and D/A conversions and a RISC/DSP core is employed for processing the digitized voice signals. The mixed signal chip is implemented in TMDP 0.6 um CMOS technology. The measured results show that all performance parameters meet ITU-T Recommendations G.712 requirements.
Sponsorship	Chinese Inst. Electron.
Starting Page	240
Ending Page	243
File Size	358530
Page Count	4
File Format	PDF
ISBN	0780366778
DOI	10.1109/ICASIC.2001.982542
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-10-23
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing Circuit simulation Codecs Digital signal processing chips Digital filters Finite impulse response filter CMOS technology Impedance matching Digital signal processing Attenuation
Content Type	Text
Resource Type	Article

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