NDLI: A methodology for high level synthesis of high performance DSP structures targetting FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Shehata, S. Haroun, B. Al-Khalili, A.
Copyright Year	1996
Description	Author affiliation: Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada (Shehata, S.)
Abstract	High level synthesis transforms a given behavioral specification into a register transfer level that can implement the given behavior. In this paper a novel technique that combines heuristics and mathematical programming formulation of the synthesis problem is introduced. This technique exploits features of the implementation hardware FPGAs and explore larger solution space than previous approaches. In this paper we particularly emphasize the importance of the optimization function that should be multi faceted. We simultaneously optimize the performance of the architecture, while minimizing the area and interconnections used in a given chip. The effect of deep pipe-lining and multi level chaining is demonstrated. The efficiency of our approach is demonstrated by comparing the results for typical high level synthesis benchmarks.
Starting Page	89
Ending Page	92
File Size	373266
Page Count	4
File Format	PDF
ISBN	7543909405
DOI	10.1109/ICASIC.1996.562758
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-10-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Digital signal processing Field programmable gate arrays Digital signal processing chips Signal synthesis Registers Mathematical programming Hardware Programmable logic arrays Acceleration
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Mr. Siddhartha Mukherjee siddhartha@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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